F-Tile CPRI PHY Multirate Intel® FPGA IP User Guide

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ID 710578
Date 1/13/2025
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Configuration Registers 7. F-Tile CPRI PHY Multirate Intel FPGA IP User Guide Archives 8. Document Revision History for the F-Tile CPRI PHY Multirate Intel® FPGA IP User Guide
1. Introduction x
1.1. IP Core Overview 1.2. Release Information 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Related Documentation
2. Interface Overview x
2.1. Clock Signals 2.2. Reset Signals 2.3. TX MII Interface (64b/66b) 2.4. RX MII Interface (64b/66b) 2.5. Status Interface for 64b/66b Line Rate 2.6. TX Interface (8b/10b) 2.7. RX Interface (8b/10b) 2.8. Status Interface for 8b/10b Line Rate 2.9. TX Tunnel Interface 2.10. Using TX Tunnel Interface 2.11. RX Tunnel Interface 2.12. Using RX Tunnel Interface 2.13. Status Interface for Tunnel Line Rate 2.14. Serial Interface 2.15. CPRI PHY Reconfiguration Interface 2.16. Datapath Avalon Memory-Mapped Interface 2.17. PMA Avalon Memory-Mapped Interface
2.1. Clock Signals x
2.1.1. Required Clock Frequencies
3. Parameters x
3.1. Analog Parameters for F-Tile IPs 3.2. Sub Profile Parameters Validation 3.3. Adaptation Parameters
4. Designing with the IP Core x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Specifying the IP Core Parameters and Options 4.3. Generated File Structure 4.4. Dynamic Reconfiguration Settings
4.1. Installing and Licensing Intel® FPGA IP Cores x
4.1.1. Intel® FPGA IP Evaluation Mode
4.2. Specifying the IP Core Parameters and Options x
4.2.1. Reference and System PLL Clock for your IP Design
5. Block Description x
5.1. Latency Measurement 5.2. CDR Clock Output 5.3. RX PMA Adaptation
5.1. Latency Measurement x
5.1.1. Deterministic Latency 5.1.2. Calculation for 64b/66b Datapath
1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Configuration Registers
7. F-Tile CPRI PHY Multirate Intel FPGA IP User Guide Archives
8. Document Revision History for the F-Tile CPRI PHY Multirate Intel® FPGA IP User Guide

3.3. Adaptation Parameters

The F-Tile CPRI PHY Multirate IP allows auto-adaptation and manual tuning.

CPRI 9.8304 Gbps unscrambled uses manual tuning. The serial loopback enable and disable sequences are the same as CPRI 6G and less. CPRI 9.8304Gbps scrambled uses auto adaptation. The serial loopback enable and disable sequences are the same as CPRI 10G and higher. You can find Tcl scripts in F Tile Dynamic Reconfiguration Design Example when you choose the CPRI variant.

Table 32.  Adaptation Parameters
Speed (gbps) Adaptation Support IP Default
Auto Manual
24.33024 with and without RS-FEC Yes No Auto-adaptation

12.1651 with and without RS-FEC

 Yes No Auto-adaptation
10.1376 with and without RS-FEC Yes No Auto-adaptation

9.8304 scrambled

 Yes No Auto-adaptation
9.8304 unscrambled No Yes Auto-adaptation 1
6.144 No Yes Manual tuning

4.9152

No Yes Manual tuning

3.072

No Yes Manual tuning

2.4576

No Yes Manual tuning

1.228

No Yes Manual tuning
Figure 10. Manual TuningThe example shows QSF assignments to use manual tuning for profile 6. 
set_instance_assignment -name HSSI_PARAMETER "flux_mode=FLUX_MODE_BYPASS" -to GEN_CPRIPHY_MR_INST[0].cpriphy_dr_ed_dut_wrapper|cpriphy_mr_dut|cpriphy_mr_f_0|profile_6|cpriphy_ftile_6|cpriphy_f_bb_inst|hip_bb|bb_f_ux_inst0|x_bb_f_ux_rx -entity cpriphy_dr_ed_hw
set_instance_assignment -name HSSI_PARAMETER "engineered_link_mode=ENABLE" -to GEN_CPRIPHY_MR_INST[0].cpriphy_dr_ed_dut_wrapper|cpriphy_mr_dut|cpriphy_mr_f_0|profile_6|cpriphy_ftile_6|cpriphy_f_bb_inst|hip_bb|bb_f_ux_inst0|x_bb_f_ux_rx -entity cpriphy_dr_ed_hw
set_instance_assignment -name HSSI_PARAMETER "rx_adapt_mode=RX_ADAPT_MODE_STATIC_EQ" -to GEN_CPRIPHY_MR_INST[0].cpriphy_dr_ed_dut_wrapper|cpriphy_mr_dut|cpriphy_mr_f_0|profile_6|cpriphy_ftile_6|cpriphy_f_bb_inst|hip_bb|bb_f_ux_inst0|x_bb_f_ux_rx -entity cpriphy_dr_ed_hw
set_instance_assignment -name HSSI_PARAMETER "flux_mode=FLUX_MODE_BYPASS" -to GEN_CPRIPHY_MR_INST[0].cpriphy_dr_ed_dut_wrapper|cpriphy_mr_dut|cpriphy_mr_f_0|profile_6|cpriphy_ftile_6|cpriphy_f_bb_inst|hip_bb|bb_f_ux_inst0|x_bb_f_ux_tx -entity cpriphy_dr_ed_hw
set_instance_assignment -name HSSI_PARAMETER "engineered_link_mode=ENABLE" -to GEN_CPRIPHY_MR_INST[0].cpriphy_dr_ed_dut_wrapper|cpriphy_mr_dut|cpriphy_mr_f_0|profile_6|cpriphy_ftile_6|cpriphy_f_bb_inst|hip_bb|bb_f_ux_inst0|x_bb_f_ux_tx -entity cpriphy_dr_ed_hw
CPRI 9.8304Gbps unscrambled uses manual tuning. The serial loopback enable and disable sequences are the same as CPRI 6G and below. CPRI 9.8304Gbps scrambled uses auto adaption. The serial loopback enable and disable sequences are the same as CPRI 10G and above. You can find tcl scripts in F Tile Dynamic Reconfiguration Example Design when choose CPRI variant.
1

You need to use QSF assignments in *.QSF to use manual tuning.

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