F-Tile CPRI PHY Multirate Intel® FPGA IP User Guide

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ID 710578
Date 8/03/2023
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Configuration Registers 7. F-Tile CPRI PHY Multirate Intel FPGA IP User Guide Archives 8. Document Revision History for the F-Tile CPRI PHY Multirate Intel® FPGA IP User Guide
1. Introduction x
1.1. IP Core Overview 1.2. Release Information 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Related Documentation
2. Interface Overview x
2.1. Clock Signals 2.2. Reset Signals 2.3. TX MII Interface (64b/66b) 2.4. RX MII Interface (64b/66b) 2.5. Status Interface for 64b/66b Line Rate 2.6. TX Interface (8b/10b) 2.7. RX Interface (8b/10b) 2.8. Status Interface for 8b/10b Line Rate 2.9. TX Tunnel Interface 2.10. Using TX Tunnel Interface 2.11. RX Tunnel Interface 2.12. Using RX Tunnel Interface 2.13. Status Interface for Tunnel Line Rate 2.14. Serial Interface 2.15. CPRI PHY Reconfiguration Interface 2.16. Datapath Avalon Memory-Mapped Interface 2.17. PMA Avalon Memory-Mapped Interface
2.1. Clock Signals x
2.1.1. Required Clock Frequencies
3. Parameters x
3.1. Sub Profile Parameters Validation
4. Designing with the IP Core x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Specifying the IP Core Parameters and Options 4.3. Generated File Structure 4.4. Dynamic Reconfiguration Settings
4.1. Installing and Licensing Intel® FPGA IP Cores x
4.1.1. Intel® FPGA IP Evaluation Mode
4.2. Specifying the IP Core Parameters and Options x
4.2.1. Reference and System PLL Clock for your IP Design
5. Block Description x
5.1. Latency Measurement 5.2. CDR Clock Output 5.3. RX PMA Adaptation
5.1. Latency Measurement x
5.1.1. Deterministic Latency 5.1.2. Calculation for 64b/66b Datapath
1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Configuration Registers
7. F-Tile CPRI PHY Multirate Intel FPGA IP User Guide Archives
8. Document Revision History for the F-Tile CPRI PHY Multirate Intel® FPGA IP User Guide

3. Parameters

You customize the IP core by specifying parameters in the IP parameter editor.
Figure 5. IP Parameter Editor
Note: The 2.4G options in the list above should be carrying the value of 2.4576G instead of 2.4376G. This is to be corrected in a future release.
Table 24.  Parameter Settings: IP Tab
Parameter Supported Values Default Setting Description
Profile 0 (Power Up)
System PLL Frequency
  • 805.664062 MHz
  • 830.078125 MHz
  • 903.125 MHz
 805.664062 MHz Select the System PLL frequency for your IP.
Enable CDR Clock Output
  • On
  • Off
 Off Turn on this parameter to enable CDR clock output. You can enable this feature only if the transceiver is placed at FGT transceiver Quad 3 or Quad 2 location.
CPRI Rate
  • 24.33024G (64b/66b) with RS-FEC
  • 24.33024G (64b/66b)
  • 12.16512G (64b/66b) with RS-FEC
  • 12.16512G (64b/66b)
  • 10.1376G (64b/66b)
  • 9.8304G (8b/10b)
  • 6.144G (8b/10b)
  • 4.9152G (8b/10b)
  • 3.072G (8b/10b)
  • 2.4576G (8b/10b)
  • 1.2288G (8b/10b)
 24.33024G (64b/66b) with RS-FEC Selects the CPRI data rate.

The hard RS-FEC block is included in the core if you select 10.1376, 12.1651, and 24.33024 Gbps (64b/66b) with the RS-FEC option.

Enable Reconfiguration to 8b/10b Datapath
  • On
  • Off
 Off Turn on this parameter if you plan to reconfigure the CPRI line rate of your channels from 64b/66b datapath rates to 8b/10b datapath rates at run-time.

If this option is not enabled, the CPRI IP core uses fewer resources, and you cannot change to 8b/10b datapath rates at run-time.
Enable Reconfiguration to Tunneling Datapath
  • On
  • Off
 Off Turn on this parameter to send and receive 32-bit raw PMA-direct data.
Dynamic Reconfiguration Options
Number of Sub Profiles 1 to 15 1 Select the number of sub profiles.
CPRI Rate for Sub Profile
  • 24.33024G (64b/66b)
  • 12.16512G (64b/66b) with RSFEC
  • 12.16512G (64b/66b)
  • 10.1376G (64b/66b) with RSFEC
  • 10.1376G (64b/66b)
  • 10.1376G (tunneling)
  • 9.8304G (8b/10b)
  • 9.8304G (tunneling)
  • 6.144G (8b/10b)
  • 4.9152G (8b/10b)
  • 4.9152G (tunneling)
  • 3.072G (8b/10b)
  • 2.4576G (8b/10b)
  • 2.4576G (tunneling)
  • 1.2288G (8b/10b)
 24.33024G (64b/66b) Selects the CPRI data rate for the sub profile.
PMA Reference Frequency
  • 153.6 MHz
  • 184.32 MHz
 184.32 MHz Only one value of the reference clock frequency is supported for each CPRI line rate:
  • For CPRI line rates that include 8b/10b soft PCS, use a reference clock of 153.6 MHz.
  • For CPRI line rates that include 64b/66b hard PCS, use a reference clock of 184.32 MHz.

Section Content
Sub Profile Parameters Validation

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