F-Tile SDI II Intel® FPGA IP Design Example User Guide

Download PDF
ID 710496
Date 10/05/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. F-Tile SDI II Intel FPGA IP Design Example Quick Start Guide 2. Design Example Detailed Description 3. F-Tile SDI II Intel FPGA IP Design Example User Guide Archives 4. Document Revision History for the F-Tile SDI II Intel® FPGA IP Design Example User Guide
1. F-Tile SDI II Intel FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design 1.3. Simulating the Design 1.4. Compiling and Testing the Design in Hardware 1.5. Design Example Parameters
1.5. Design Example Parameters x
1.5.1. Design Example Presets
2. Design Example Detailed Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Hardware Testing 2.6. Interface Signal
2.3. Functional Description x
2.3.1. Design Components 2.3.2. Clocking Scheme
2.3.2. Clocking Scheme x
2.3.2.1. Clocking Scheme Components
2.4. Simulation x
2.4.1. Testbench Components 2.4.2. Test Description
2.5. Hardware Testing x
2.5.1. Parallel loopback 2.5.2. Serial loopback
1. F-Tile SDI II Intel FPGA IP Design Example Quick Start Guide
2. Design Example Detailed Description
3. F-Tile SDI II Intel FPGA IP Design Example User Guide Archives
4. Document Revision History for the F-Tile SDI II Intel® FPGA IP Design Example User Guide

2.1. Features

  1. LED status for early debugging stage with RX- or TX-only options.
  2. To use RX- or TX-only components, remove the irrelevant blocks from the simplex version serial loopback design as described in the following table.
    Table 6.  Features
    User Requirement Preserve Remove
    RX only
    • RX top
    • Reference and System PLL Clocks IP
    • DR IP & DR arbiter (if present)
    • Sys Reset
    		 TX Top
    TX only
    • TX top
    • Reference and System PLL Clocks IP
    • DR IP & DR arbiter (if present)
    • Sys Reset
    		 RX Top
Figure 13. Components Required for TX- or RX-Only Design on Intel Agilex® 7 Devices
Note: Refer to Clocking Scheme for the Reference and System PLL Clocks IP connections.
Level Two Title