F-Tile SDI II Intel® FPGA IP Design Example User Guide
ID
710496
Date
10/05/2023
Public
A newer version of this document is available. Customers should click here to go to the newest version.
2. Design Example Detailed Description
The SDI II Intel® FPGA IP core includes the following design examples for Intel Agilex® 7 F-Tile devices.
- Parallel loopback with external VCXO
- Parallel loopback without external VCXO
- Serial loopback
Note: The Serial loopback design is not supported when you select AXIS-VVP Full active video data protocol.