F-Tile DisplayPort Intel® FPGA IP Design Example User Guide

ID 709308
Date 6/06/2024
Document Table of Contents

1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide

Updated for:
Intel® Quartus® Prime Design Suite 24.1
IP Version 20.0.1
The DisplayPort Intel® FPGA IP design examples for Agilex™ 7 F-Tile devices feature a preliminary simulation testbench and a hardware design that supports compilation and hardware testing.
The DisplayPort Intel® FPGA IP offers the following design examples:
  • DisplayPort SST parallel loopback without a Pixel Clock Recovery (PCR) module
  • DisplayPort SST parallel loopback with AXIS Video Interface
  • DisplayPort SST RX-only
  • DisplayPort SST TX-only
When you generate a design example, the parameter editor automatically creates the files necessary to simulate, compile, and test the design in hardware.
Note: A design example might not be enabled if the selected IP options are incompatible with the example design. For example, if the DisplayPort Source is enabled, then the RX-only design will not be available. Refer to the DisplayPort Intel FPGA IP Design Example Parameters for Intel Agilex 7 F-Tile Device table for the required IP settings.
Figure 1. Development Stages