F-Tile DisplayPort Intel® FPGA IP Design Example User Guide

Download PDF
ID 709308
Date 4/18/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide 2. Parallel Loopback Design Examples 3. HDCP Over DisplayPort Design Example for Intel Agilex® 7 Devices 4. Document Revision History for F-Tile DisplayPort Intel FPGA IP Design Example User Guide
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Hardware and Software Requirements 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design 1.6. DisplayPort Intel® FPGA IP Design Example Parameters
1.5. Compiling and Testing the Design x
1.5.1. Regenerating ELF File
2. Parallel Loopback Design Examples x
2.1. Intel Agilex® 7 F-tile DisplayPort SST Parallel Loopback Design Features 2.2. Design Components 2.3. Clocking Scheme 2.4. Interface Signals and Parameters 2.5. Simulation Testbench
3. HDCP Over DisplayPort Design Example for Intel Agilex® 7 Devices x
3.1. High-bandwidth Digital Content Protection (HDCP) 3.2. HDCP Over DisplayPort Design Example Architecture 3.3. Nios II Processor Software Flow 3.4. Design Walkthrough 3.5. Protection of Encryption Key Embedded in FPGA Design 3.6. Debug Guidelines
3.4. Design Walkthrough x
3.4.1. Set Up the Hardware 3.4.2. Generate the Design 3.4.3. Include HDCP Production Keys 3.4.4. Compile the Design 3.4.5. View the Results
3.4.3. Include HDCP Production Keys x
3.4.3.1. Store plain HDCP production keys in the FPGA (Support HDCP Key Management = 0) 3.4.3.2. Store encrypted HDCP production keys in the external flash memory or EEPROM (Support HDCP Key Management = 1)
3.4.3.1. Store plain HDCP production keys in the FPGA (Support HDCP Key Management = 0) x
3.4.3.1.1. HDCP Key Mapping from DCP Key Files 3.4.3.1.2. hdcp1x_tx_kmem.v and hdcp1x_rx_kmem.v files 3.4.3.1.3. hdcp2x_rx_kmem.v file 3.4.3.1.4. hdcp2x_tx_kmem.v file
3.4.3.2. Store encrypted HDCP production keys in the external flash memory or EEPROM (Support HDCP Key Management = 1) x
3.4.3.2.1. Intel KEYENC 3.4.3.2.2. Key Programmer
3.4.5. View the Results x
3.4.5.1. LED Functions
3.5. Protection of Encryption Key Embedded in FPGA Design x
3.5.1. Security Considerations
3.6. Debug Guidelines x
3.6.1. HDCP Status Signals 3.6.2. Modifying HDCP Software Parameters 3.6.3. Frequently Asked Questions (FAQ)
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide
2. Parallel Loopback Design Examples
3. HDCP Over DisplayPort Design Example for Intel Agilex® 7 Devices
4. Document Revision History for F-Tile DisplayPort Intel FPGA IP Design Example User Guide

2.3. Clocking Scheme

The clocking scheme illustrates the clock domains in the DisplayPort Intel FPGA IP design example.

Figure 8.  Intel Agilex® 7 F-tile DisplayPort Transceiver clocking scheme
Table 8.  Clocking Scheme Signals
Clock in diagram Description
SysPLL refclk

F-tile System PLL reference clock which can be any clock frequency that is dividable by System PLL for that output frequency.

In this design example, system_pll_clk_link and rx/tx refclk_link share the same 150 MHz SysPLL refclk.

It must be a free running clock which is connected from a dedicated transceiver reference clock pin to the input clock port of Reference and System PLL Clocks IP, before connecting the corresponding output port to DisplayPort Phy Top.

Note: For this design example, configure Clock Controller GUI Si5391A OUT6 to 150 MHz.
system_pll_clk_link

The minimum System PLL output frequency to support all DisplayPort rates is 320 MHz.

This design example uses a 900 MHz (highest) output frequency so that SysPLL refclk can be shared with rx/tx refclk_link, which is 150 MHz.

rx_cdr_refclk_link /

tx_pll_refclk_link 		Rx CDR and Tx PLL Link refclk which is fixed to 150 MHz to support all DisplayPort data rates.

rx_ls_clkout /

tx_ls_clkout

DisplayPort Link Speed Clock to clock DisplayPort IP core. The frequency is equivalent to Data Rate divided by parallel data width.

Example:

Frequency = data rate / data width

For HBR3:

= 8.1G (HBR3) / 40 bits

= 202.5 MHz

For UHBR10:

= 10G (UHBR10) / 32 bits

= 312.5 MHz

Note: For UHBR, DisplayPort Parallel width is in 32 bits
Level Two Title