DisplayPort Stratix® 10 FPGA IP Design Example User Guide

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ID 683887
Date 4/10/2024
Public
Document Table of Contents
Document Table of Contents x
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide 2. Parallel Loopback Design Examples 3. HDCP Over DisplayPort Design Example 4. DisplayPort Stratix® 10 FPGA IP Design Example User Guide Archives 5. Revision History for the DisplayPort Stratix® 10 FPGA IP Design Example User Guide
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Hardware and Software Requirements 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design 1.6. DisplayPort Intel® FPGA IP Design Example Parameters
1.5. Compiling and Testing the Design x
1.5.1. Regenerating ELF File
2. Parallel Loopback Design Examples x
2.1. Stratix® 10 DisplayPort SST Parallel Loopback Design Features 2.2. Stratix® 10 DisplayPort SST TX-only or RX-only Design Features 2.3. Design Components 2.4. Clocking Scheme 2.5. Interface Signals and Parameters 2.6. Hardware Setup 2.7. Simulation Testbench 2.8. DisplayPort Transceiver Reconfiguration Flow 2.9. Transceiver Lane Configurations
2.1. Stratix® 10 DisplayPort SST Parallel Loopback Design Features x
2.1.1. DisplayPort 2.0 UHBR10 (10 Gbps) Data Rate Support 2.1.2. DisplayPort 2.0 UHBR20 (20 Gbps) Data Rate Support 2.1.3. Enabling Adaptive Sync Support
2.2. Stratix® 10 DisplayPort SST TX-only or RX-only Design Features x
2.2.1. Stratix® 10 DisplayPort SST TX-only Design Features 2.2.2. Stratix® 10 DisplayPort SST RX-only Design Features
3. HDCP Over DisplayPort Design Example x
3.1. High-bandwidth Digital Content Protection (HDCP) 3.2. HDCP Over DisplayPort Design Example Architecture 3.3. Nios® V Processor Software Flow 3.4. Design Walkthrough 3.5. Protection of Encryption Key Embedded in FPGA Design 3.6. Debug Guidelines
3.4. Design Walkthrough x
3.4.1. Setting Up the Hardware 3.4.2. Generating the Design 3.4.3. Including HDCP Production Keys 3.4.4. Compiling the Design 3.4.5. Viewing the Results
3.4.3. Including HDCP Production Keys x
3.4.3.1. Storing Plain HDCP Production Keys in the FPGA (Support HDCP Key Management = 0) 3.4.3.2. Storing Encrypted HDCP Production Keys in the External Flash Memory or EEPROM (Support HDCP Key Management = 1)
3.4.3.1. Storing Plain HDCP Production Keys in the FPGA (Support HDCP Key Management = 0) x
3.4.3.1.1. HDCP Key Mapping from DCP Key Files 3.4.3.1.2. hdcp1x_tx_kmem.v and hdcp1x_rx_kmem.v files 3.4.3.1.3. hdcp2x_rx_kmem.v file 3.4.3.1.4. hdcp2x_tx_kmem.v file
3.4.3.2. Storing Encrypted HDCP Production Keys in the External Flash Memory or EEPROM (Support HDCP Key Management = 1) x
3.4.3.2.1. Intel KEYENC 3.4.3.2.2. Key Programmer
3.5. Protection of Encryption Key Embedded in FPGA Design x
3.5.1. Security Considerations
3.6. Debug Guidelines x
3.6.1. HDCP Status Signals 3.6.2. Modifying HDCP Software Parameters 3.6.3. Frequently Asked Questions (FAQ)
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide
2. Parallel Loopback Design Examples
3. HDCP Over DisplayPort Design Example
4. DisplayPort Stratix® 10 FPGA IP Design Example User Guide Archives
5. Revision History for the DisplayPort Stratix® 10 FPGA IP Design Example User Guide

2.1.1. DisplayPort 2.0 UHBR10 (10 Gbps) Data Rate Support

The DisplayPort 2.0 supports new data rate up to 10 Gbps (UHBR10) and it supports backward compatibility to any DisplayPort 1.4 data rates. In this release, the only design example variant supported is the DisplayPort SST parallel loopback without PCR.

To support the DisplayPort 2.0 UHBR10 data rate:

  • Select MAX_LINK_RATE to 10 Gbps to enable DisplayPort 2.0.
  • Enable TX_SUPPORT_IM_ENABLE to generate the design example variant without PCR.
  • New transceiver refclk of 100 MHz is required to support 10 Gbps.
    • Refclk switching is required during the data rate switching.
  • FMC card supporting DisplayPort 2.0: Bitec FMC Revision 8 only.

Selecting MAX_LINK_RATE 10 Gbps fixes SYMBOLS_PER_CLOCK to 4. The DisplayPort Intel® FPGA IP supporting the MAX_LINK_RATE 10 Gbps exports 40 bits data width of rx/tx_parallel_data per channel. The DisplayPort Intel® FPGA IP will remap the parallel data width to 8B/10B channel coding data path and 128B/132B channel coding data path, respectively.

Selecting MAX_LINK_RATE 10 Gbps enables RX_GPU_MODE by default. The DisplayPort 2.0 sink is only supported in the GPU mode which requires the Nios® controller and Software Sink API.

In the software/dp_demo folder, rx_utils.c has updated the Sink DPCP capability register to support DisplayPort 2.0. The table below lists the DPCD registers.

Table 8.  DPCD Registers
DPCD Register Address Bit Description Design Example Default Value
0x0006h/0x2206h MAIN_LINK_CHANNEL_CODING_CAP
  • 0 = Not supported.
  • 1 = Supported.
0

8b10b_DP_SUPPORTED

Mandated to be set to 1.

 1’b1
1 128b132b_DP_SUPPORTED

Set for DPRXs that support 128b/132b DP Link Layer.

 1’b1
0x2215h

128b132b_SUPPORTED_LINK_RATES

Valid only when the 128b132b_DP_SUPPORTED bit in the MAIN_LINK_CHANNEL_CODING_CAP register is set (DPCD 0x2206h[1] = 1), for 128b/132b DP Link Layer.

0

10 Gbps per Lane Support

Indicates whether the link rate associated with UHBR10 is supported.

  • 0 = Not supported.
  • 1 = Supported. Support for this link rate is mandatory for the 128b/132b DP Link Layer-capable DP devices.

1’b1 (support 10Gbps)

1

20 Gbps per Lane Support

Indicates whether the link rate associated with UHBR20 is supported.

  • 0 = Not supported.
  • 1 = Supported. Highest link rate available. Support is optional.

1’b0 (not supported)

2

13.5 Gbps per Lane Support

Indicates whether the link rate associated with UHBR13.5 is supported.

  • 0 = Not supported.
  • 1 = Supported. Support is optional.
Note: Support for 13.5 Gbps/lane is optional, even for a DPRX that supports 20 Gbps/lane.

1’b0 (not supported)

0x2216h

128b132b_DP_TRAINING_AUX_RD_INTERVAL

Valid only for 128b/132b DP Link Layer.
6:1

128b132b_DP_TRAINING_AUX_RD_INTERVAL

Updated through SCRs in DP v2.0 Errata E10.

Link Status/Adjust Request read interval during Main-Link training sequences.

The interval is (128b132b_DP_TRAINING_AUX_RD_INTERVAL value + 1) × 128b132b_DP_TRAINING_AUX_RD_INTERVAL_UNIT

The maximum is 256 ms.

7’h3F (128ms selected)

0

128b132b_DP_TRAINING_AUX_RD_INTERVAL_UNIT

New through SCRs in DP v2.0 Errata E10.

  • 0 = 2 ms.
  • 1 = 1 ms.
 1’b1
Level Two Title