F-Tile Avalon® Streaming IP for PCI Express* Release Notes

Download PDF
ID 683886
Date 9/29/2025
Public
Document Table of Contents
Document Table of Contents x
1. F-Tile Avalon Streaming Intel FPGA IP for PCI Express* Release Notes
1. F-Tile Avalon Streaming Intel FPGA IP for PCI Express* Release Notes x
1.1. F-Tile Avalon® Streaming IP for PCI Express: IP Core v12.4.0 1.2. F-Tile Avalon® Streaming IP for PCI Express: IP Core v12.3.0 1.3. F-Tile Avalon® Streaming IP for PCI Express : IP Core v12.2.0 1.4. F-Tile Avalon Streaming IP for PCI Express: IP Core v12.1.0 1.5. F-Tile Avalon Streaming IP for PCI Express : IP Core v12.0.0 1.6. F-Tile Avalon Streaming IP for PCI Express : IP Core v11.0.0 1.7. F-Tile Avalon Streaming IP for PCI Express : IP Core v10.0.0 1.8. F-Tile Avalon Streaming IP for PCI Express : IP Core v9.0.0 1.9. F-Tile Avalon Streaming IP for PCI Express : IP Core v8.1.0 1.10. F-Tile Avalon Streaming IP for PCI Express : IP Core v8.0.0 1.11. F-Tile Avalon Streaming IP for PCI Express : IP Core v7.0.0 1.12. F-Tile Avalon Streaming IP for PCI Express : IP Core v6.0.0 1.13. F-Tile Avalon Streaming IP for PCI Express : IP Core v5.0.0 1.14. F-Tile Avalon Streaming IP for PCI Express : IP Core v4.0.0 1.15. F-Tile Avalon Streaming IP for PCI Express : IP Core v3.0.0 1.16. F-Tile Avalon Streaming IP for PCI Express : IP Core v2.0.0 1.17. F-Tile Avalon Streaming IP for PCI Express : User Guide Archives
1. F-Tile Avalon Streaming Intel FPGA IP for PCI Express* Release Notes

1.8. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v8.1.0

Table 8.  v8.1.0 2023.04.17
Quartus® Prime Version Description Impact
23.1

The preset or default value for Gen 3 Requested equalization farend TX preset vector and Gen 4 Requested equalization far-end TX preset vector has been updated in the IP Parameter Editor GUI.

The new preset or default values are recommended for most designs.

You should update the preset value to the new one if the F-Tile PCIe IP was generated in the previous Quartus® Prime software version that uses the old default value.

Added Intel Agilex® 7 F-Tile FPGA Development Kit with rev B0 silicon board preset for design example generation.

The VID-related settings including the pin assignments are included in the .qsf file of the generated design example when selected.

Level Two Title