F-Tile Avalon® Streaming IP for PCI Express* Release Notes

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ID 683886
Date 9/29/2025
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1. F-Tile Avalon Streaming Intel FPGA IP for PCI Express* Release Notes
1. F-Tile Avalon Streaming Intel FPGA IP for PCI Express* Release Notes x
1.1. F-Tile Avalon® Streaming IP for PCI Express: IP Core v12.4.0 1.2. F-Tile Avalon® Streaming IP for PCI Express: IP Core v12.3.0 1.3. F-Tile Avalon® Streaming IP for PCI Express : IP Core v12.2.0 1.4. F-Tile Avalon Streaming IP for PCI Express: IP Core v12.1.0 1.5. F-Tile Avalon Streaming IP for PCI Express : IP Core v12.0.0 1.6. F-Tile Avalon Streaming IP for PCI Express : IP Core v11.0.0 1.7. F-Tile Avalon Streaming IP for PCI Express : IP Core v10.0.0 1.8. F-Tile Avalon Streaming IP for PCI Express : IP Core v9.0.0 1.9. F-Tile Avalon Streaming IP for PCI Express : IP Core v8.1.0 1.10. F-Tile Avalon Streaming IP for PCI Express : IP Core v8.0.0 1.11. F-Tile Avalon Streaming IP for PCI Express : IP Core v7.0.0 1.12. F-Tile Avalon Streaming IP for PCI Express : IP Core v6.0.0 1.13. F-Tile Avalon Streaming IP for PCI Express : IP Core v5.0.0 1.14. F-Tile Avalon Streaming IP for PCI Express : IP Core v4.0.0 1.15. F-Tile Avalon Streaming IP for PCI Express : IP Core v3.0.0 1.16. F-Tile Avalon Streaming IP for PCI Express : IP Core v2.0.0 1.17. F-Tile Avalon Streaming IP for PCI Express : User Guide Archives
1. F-Tile Avalon Streaming Intel FPGA IP for PCI Express* Release Notes

1.5. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v11.0.0

Table 5.  v11.0.0 2024.01.29
Quartus® Prime Version Description Impact
23.4

The default Gen 4 Requested equalization far-end TX preset vector is changed to P5/6/8/9(0x00000360) with P1 and P3 being removed compared to previous releases.

The equalization process of link training is expected to improve.

For simulation in PIPE mode, o_p1_prot_f2t_ssr[18:3] is available for users to generate PIPE reset to the VIP.

This allows users to reset the VIP during PIPE mode simulation.

Introduction of PCIe Receiver Detection new tab.

It is optional for the PCIe controller to ignore receiver detection from PHY during LTSSM Detect state and user-defined value.
Level Two Title