F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Release Notes

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Date 1/29/2024
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1. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Release Notes
1. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Release Notes x
1.1. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v11.0.0 1.2. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v10.0.0 1.3. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v9.0.0 1.4. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v8.1.0 1.5. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v8.0.0 1.6. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v7.0.0 1.7. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v6.0.0 1.8. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v5.0.0 1.9. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v4.0.0 1.10. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v3.0.0 1.11. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v2.0.0 1.12. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : User Guide Archives
1. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Release Notes

1.7. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v6.0.0

Table 7.  F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP v6.0.0 : 2022.06.23
Intel® Quartus® Prime Version Description Impact
22.2

Added Hard IP Reconfiguration Interface support when Debug Toolkit is enabled and included bug fixes for Debug Toolkit

Hard IP Reconfiguration Interface option is now available when the Debug Toolkit is enabled in the IP Parameter Editor.

The Hard IP Reconfiguration Interface is accessible whenever the Debug Toolkit is not active.

“Strip ECRC” option has been introduced when the IP is configured in TLP-Bypass mode.

Allows users to disable ECRC in TLP-Bypass mode.

“Enable Hard IP Reconfiguration Interface” option has been moved under PCIe Avalon Settings tab.

No impact to existing users other than the IP option relocation in IP Parameter Editor.
Added the following new Hard IP Mode support:
  • Gen4 1x16 Interface – 512 bit (PLD Clock Frequency 175 MHz / 200 MHz / 225 MHz / 250 MHz)
  • Gen3 1x16, Interface - 256 bit (PLD Clock Frequency 250 MHz)
  • Gen4, 2x8, Interface - 512 bit (PLD Clock Frequency 175 MHz / 200 MHz / 225 MHz / 250 MHz)
  • Gen4, 2x8, Interface - 256 bit (PLD Clock Frequency 175 MHz / 200 MHz / 225 MHz / 250 MHz)

Provides more flexibility for user logic interfacing with F-Tile Avalon-ST PCIe Hard IP and seamless migration path from P-Tile Avalon-ST PCIe Hard IP.

Reduced warning messages for the F-Tile Avalon-ST PCIe Hard IP and its design examples

Allows users to focus on warning messages that require their attention.

Added F-Tile Performance design example variant.

Performance design example may be used to demonstrate F-Tile functionality with multiple TLPs per cycle.

Added FASTSIM mode support to shorten the F-Tile Avalon-ST PCIe Hard IP simulation time.

The FASTSIM mode is disabled by default. It is enabled through a predefined simulation option. Users have an option to simulate with or without FASTSIM mode.

Fixed simulation issue for F-Tile Avalon-ST PCIe Hard IP SR-IOV Design Example variant.

Use Intel® Quartus® Prime Pro Edition v22.2 and onwards to generate F-Tile Avalon-ST PCIe Hard IP SR-IOV Design Example variant for simulation to avoid unexpected error messages.

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