F-Tile Architecture and PMA and FEC Direct PHY IP User Guide
ID
683872
Date
8/04/2025
Public
1. F-Tile Overview
2. F-Tile Architecture
3. Implementing the F-Tile PMA/FEC Direct PHY IP
4. Implementing the F-Tile Reference and System PLL Clocks IP
5. F-Tile PMA/FEC Direct PHY Design Implementation
6. Supported Tools
7. Debugging F-Tile Transceiver Links
8. F-Tile Architecture and PMA and FEC Direct PHY IP User Guide Archives
9. Document Revision History for the F-Tile Architecture and PMA and FEC Direct PHY IP User Guide
A. Appendix
2.1.1. FHT and FGT PMAs
2.1.2. 400G Hard IP and 200G Hard IP
2.1.3. PMA Data Rates
2.1.4. FEC Architecture
2.1.5. PCIe* Hard IP
2.1.6. Bonding Architecture
2.1.7. Deskew Logic
2.1.8. Embedded Multi-die Interconnect Bridge (EMIB)
2.1.9. IEEE 1588 Precision Time Protocol for Ethernet
2.1.10. Clock Networks
2.1.11. Reconfiguration Interfaces
2.2.1. PMA-to-Fracture Mapping
2.2.2. Determining Which PMA to Map to Which Fracture
2.2.3. Hard IP Placement Rules
2.2.4. IEEE 1588 Precision Time Protocol Placement Rules
2.2.5. Topologies
2.2.6. FEC Placement Rules
2.2.7. Clock Rules and Restrictions
2.2.8. Bonding Placement Rules
2.2.9. Preserving Unused PMA Lanes
2.2.2.1. Implementing One 200GbE-4 Interface with 400G Hard IP and FHT
2.2.2.2. Implementing One 200GbE-2 Interface with 400G Hard IP and FHT
2.2.2.3. Implementing One 100GbE-1 Interface with 400G Hard IP and FHT
2.2.2.4. Implementing One 100GbE-4 Interface with 400G Hard IP and FGT
2.2.2.5. Implementing One 10GbE-1 Interface with 200G Hard IP and FGT
2.2.2.6. Implementing Three 25GbE-1 Interfaces with 400G Hard IP and FHT
2.2.2.7. Implementing One 50GbE-1 and Two 25GbE-1 Interfaces with 400G Hard IP and FHT
2.2.2.8. Implementing One 100GbE-1 and Two 25GbE-1 Interfaces with 400G Hard IP and FHT
2.2.2.9. Implementing Two 100GbE-1 and One 25GbE-1 Interfaces with 400G Hard IP and FHT
2.2.2.10. Implementing 100GbE-1, 100GbE-2, and 50GbE-1 Interfaces with 400G Hard IP and FHT
3.1. F-Tile PMA/FEC Direct PHY IP Overview
3.2. Designing with F-Tile PMA/FEC Direct PHY IP
3.3. Configuring the IP
3.4. Signal and Port Reference
3.5. Bit Mapping for PMA and FEC Mode PHY TX and RX Datapath
3.6. Clocking
3.7. Custom Cadence Generation Ports and Logic
3.8. Asserting Reset
3.9. Bonding Implementation
3.10. Independent Port Configurations
3.11. Configuration Registers
3.12. Configurable Quartus® Prime Software Settings
3.13. Configuring the F-Tile PMA/FEC Direct PHY IP for Hardware Testing
3.14. Hardware Configuration Using the Avalon® Memory-Mapped Interface
3.3.1. General and Common Datapath Options
3.3.2. TX Datapath Options
3.3.3. RX Datapath Options
3.3.4. RS-FEC (Reed Solomon Forward Error Correction) Options
3.3.5. Avalon® Memory Mapped Interface Options
3.3.6. Register Map IP-XACT Support
3.3.7. Example Design Generation
3.3.8. Analog Parameter Options
3.4.1. TX and RX Parallel and Serial Interface Signals
3.4.2. TX and RX Reference Clock and Clock Output Interface Signals
3.4.3. Reset Signals
3.4.4. RS-FEC Signals
3.4.5. Custom Cadence Control and Status Signals
3.4.6. TX PMA Control Signals
3.4.7. RX PMA Status Signals
3.4.8. TX and RX PMA and Core Interface FIFO Signals
3.4.9. PMA Avalon® Memory Mapped Interface Signals
3.4.10. Datapath Avalon® Memory Mapped Interface Signals
3.5.1. Parallel Data Mapping Information
3.5.2. TX and RX Parallel Data Mapping Information for Different Configurations
3.5.3. Example of TX Parallel Data for PMA Width = 8, 10, 16, 20, 32 (X=1)
3.5.4. Example of TX Parallel Data for PMA width = 64 (X=2)
3.5.5. Example of TX Parallel Data for PMA width = 64 (X=2) for FEC Direct Mode
3.8.1. Reset Signal Requirements
3.8.2. Power On Reset Requirements
3.8.3. Reset Signals—Block Level
3.8.4. Reset Signals—Descriptions
3.8.5. Status Signals—Descriptions
3.8.6. Run-time Reset Sequence—TX
3.8.7. Run-time Reset Sequence—RX
3.8.8. Run-time Reset Sequence—TX + RX
3.8.9. Run-time Reset Sequence—TX with FEC
4.1. IP Parameters
4.2. IP Port List
4.3. Mode of System PLL - System PLL Reference Clock and Output Frequencies
4.4. Guidelines for F-Tile Reference and System PLL Clocks IP Usage
4.5. Guidelines for Refclk #i is Active At and After Device Configuration
4.6. Guidelines for Obtaining the Lock Status and Resetting the FGT and FHT TX PLLs
5.1. Implementing the F-Tile PMA/FEC Direct PHY Design
5.2. Instantiating the F-Tile PMA/FEC Direct PHY IP
5.3. Implementing a RS-FEC Direct Design in the F-Tile PMA/FEC Direct PHY IP
5.4. Instantiating the F-Tile Reference and System PLL Clocks IP
5.5. Enabling Custom Cadence Generation Ports and Logic
5.6. Connecting the F-Tile PMA/FEC Direct PHY Design IP
5.7. Simulating the F-Tile PMA/FEC Direct PHY Design
5.8. F-Tile Interface Planning
5.9. Compiling a F-Tile Design with VHDL Configuration File as the Top Level Module
7.2.1. Modifying the Design to Enable F-Tile Transceiver Debug
7.2.2. Programming the Design into an Altera FPGA
7.2.3. Loading the Design to the Transceiver Toolkit
7.2.4. Creating Transceiver Links
7.2.5. Running BER Tests
7.2.6. Running Eye Viewer Tests
7.2.7. Running Link Optimization Tests
7.2.8. Checking FEC Statistics
7.2.9. Vertical Bathtub Curve Measurements (VBCM) Data
A.1. Agilex™ 7 F-Tile OPNs
A.2. OSC_CLK_1 QSF Assignment Requirement
A.3. FGT Internal Serial Loopback Sequence for RX Manual Tuning ( Quartus® Prime Pro Edition Software Versions Before 25.1.1)
A.4. FGT Internal Serial Loopback Sequence for RX Manual Tuning ( Quartus® Prime Pro Edition Software Versions from 25.1.1 Onwards)
A.5. Transceiver Toolkit Helper Script
A.6. F-Tile Tuning Guidelines
A.6.6.3.1. Example 1 : F-Tile FHT 106 Gbps PAM4 Design (Short Reach)
A.6.6.3.2. Example 2 : F-Tile FHT 106 Gbps PAM4 Design (Long Reach)
A.6.6.3.3. Example 3 : F-Tile FHT 25 Gbps NRZ Design (Short Reach)
A.6.6.3.4. Example 4 : F-Tile FHT 50 Gbps PAM4 Design (Short Reach)
A.6.6.3.5. Example 5 : F-Tile FHT 106 Gbps PAM4 Design (Short Reach)
A.6.6.3.6. Example 6 : F-Tile FHT 106 Gbps PAM4 Design (Long Reach)
A.6.6.3.7. Example 7 : F-Tile FHT 25 Gbps NRZ Design (Short Reach)
A.6.6.3.8. Example 8 : F-Tile FHT 25 Gbps NRZ Design (Long Reach)
A.6.6.3.9. Example 9 : F-Tile FHT 50 Gbps PAM4 Design (Short Reach)
A.6.6.3.10. Example 10 : F-Tile FHT 50 Gbps PAM4 Design (Long Reach)
7.3. Transceiver Toolkit Parameter Settings
The following table describes the transceiver toolkit parameter settings.
Parameter | Description | Control Pane | |
---|---|---|---|
Auto refresh RX CDR status | Enable this option to update the RX CDR status real time. | Receiver pane. | |
Auto refresh RX PMA settings | Enable this option to update the RX Equalization settings real time for FGT PMA. | Receiver pane. | |
Auto refresh TX Status | Enable this option to update the TX PLL lock status real time. | Transmitter pane | |
Bit error rate (BER) | Reports the number of errors divided by bits tested since the last reset of the checker. When RX CDR is locked to reference clock or PRBS checker is not locked, the BER reported is not reliable. | Receiver pane | |
Clear Stats | Clear the current number of bits tested, number of error bits and BER. | Receiver pane | |
Hard PRBS checker running | Not Running: checker stops. Running: checker is checking, and data pattern is locked. |
Receiver pane | |
Hard PRBS generator running | Not Running: generator stops. Running: generator is sending a pattern. |
Transmitter pane | |
Inject Error | Inject a bit error in the transmitter PRBS pattern. | Transmitter pane | |
Line encoding | Specifies the modulation type used for serial data. | Transmitter and receiver pane | |
Loopback mode | Select the loopbacks mode. The available options are:
|
Transmitter and receiver pane | |
Number of bits tested | Specifies the number of bits tested since the last reset of the checker. When RX CDR is locked to reference clock or PRBS checker is not locked, the BER reported is not reliable | Receiver pane | |
Number of error bits | Specifies the number of error bits encountered since the last reset of the checker. When RX CDR is locked to reference clock or PRBS checker is not locked, the BER reported is not reliable | Receiver pane | |
PRBS locked | Locked: indicates the PRBS checker is locked to the received PRBS pattern. Not Locked: indicates the PRBS checker is not locked to the received PRBS pattern. |
Receiver pane | |
PRBS pattern | Select the test pattern for the bit error test. | Transmitter and receiver pane | |
RX CDR locked to ref clock | Locked: Indicates the receiver CDR is in lock-to-reference (LTR) mode. Not Locked: Indicates the receiver CDR is not locked to reference clock. Don't Care: When the receiver CDR is in LTD mode. |
Receiver pane | |
RX CDR locked to data | Locked: Indicates the receiver CDR is in lock-to-data (LTD) mode. Not Locked: Indicates the receiver CDR is not locked to incoming data. |
Receiver pane | |
RX Enable Gray Code | Enables Gray coding for PAM4 only. | Receiver pane | |
RX PMA Settings | RX Equalization settings. | Receiver pane | |
RX Polarity Inversion | Enable RX polarity inversion. | Receiver pane | |
RX Ready | Ready: RX channel out of reset and CDR locks to data. Not Ready: RX channel in reset or CDR is not locked to data. |
Receiver pane | |
RX Reset FGT PMA | Reset the FGT RX datapath.
Note: Clicking the RX reset of one channel resets all the RX channels in the same F-Tile PMA/FEC Direct PHY IP instance.
|
Receiver pane | |
High Frequency VGA Gain | Options for the RX EQ VGA gain value, in 1.0 step size increments. | Receiver Pane | |
High Frequency Boost | Options for the RX EQ high frequency boost value, in 1.0 step size increments. | Receiver Pane | |
DFE Data Tap1 | Options for RX EQ DFE data tap1 value, in 1.0 step size increments. | Receiver Pane | |
Auto refresh RX PMA settings above | Enable this option to automatically update the RX PMA settings in real time. | Receiver Pane | |
Save Eye data as CSV | Set the file path to save the eye viewer data. | Receiver Pane | |
Eye Width | Enable this option for measurement of eye width. | Receiver Pane | |
Eye Height | Enable this option for measurement of eye height. | Receiver Pane | |
Bit error rate to measure Eye Height | Sets the Bit Error Rate to measure eye height. | Receiver Pane | |
Bit error rate to measure Eye Width | Sets the Bit Error Rate to measure eye width. | Receiver Pane | |
Start Eye Viewer | Starts the Eye Viewer measurements. | Receiver Pane | |
Eye Height (VBCM) | Enable this option for VBCM data measurement of eye height. | Receiver Pane | |
Eye Width (VBCM) | Enable this option for VBCM data measurement of eye width. FGT PMA only. | Receiver Pane | |
Bit error rate for Eye Height | Sets the Bit Error Rate to measure eye height. | Receiver Pane | |
Bit error rate for Eye Width | Sets the Bit Error Rate to measure eye width. FGT PMA only. | Receiver Pane | |
Export VBCM data to XLSX | Exports the VBCM data to the set working directory. | Receiver Pane | |
Start | Starts the pattern generator or checker on the channel to verify incoming data. | Transmitter and receiver pane | |
Stop | Stops generating patterns and testing the channel. | Transmitter and receiver pane | |
TX Enable Gray Code | Enables Gray coding for PAM4 only. | Transmitter pane | |
TX Equalization Parameters | FGT 48 | FHT 49 50 | Transmitter pane and receiver pane |
Post_tap_1 Main_tap Pre_tap_1 Pre_tap_2 |
C-3: Pre-cursor 3 C-2: Pre-cursor 2 C-1: Pre-cursor 1 C0: Main cursor C+1: Post-cursor 1 C+2: Post-cursor 2 C+3: Post-cursor 3 C+4: Post-cursor 4 |
||
TX PLL Locked | Locked: Indicates TX PLL locks to reference clock. | Transmitter pane | |
TX Polarity Inversion | Enable TX polarity inversion. | Transmitter pane | |
TX Reset FGT PMA | Reset the FGT TX PMA datapath.
Note: Clicking the TX reset of one channel resets all the TX channels in the same F-Tile PMA/FEC Direct PHY IP instance.
|
Transmitter pane |
48 Refer to F-Tile TX Equalizer Tool for legal settings.
49 Refer to FHT PMA Architecture for legal settings.
50 When internal serial loopback is enabled, the TX Equalization Parameters are set to default values.