F-Tile Architecture and PMA and FEC Direct PHY IP User Guide

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ID 683872
Date 8/04/2025
Public
Document Table of Contents
Document Table of Contents x
1. F-Tile Overview 2. F-Tile Architecture 3. Implementing the F-Tile PMA/FEC Direct PHY IP 4. Implementing the F-Tile Reference and System PLL Clocks IP 5. F-Tile PMA/FEC Direct PHY Design Implementation 6. Supported Tools 7. Debugging F-Tile Transceiver Links 8. F-Tile Architecture and PMA and FEC Direct PHY IP User Guide Archives 9. Document Revision History for the F-Tile Architecture and PMA and FEC Direct PHY IP User Guide A. Appendix
1. F-Tile Overview x
1.1. Device Family Support
2. F-Tile Architecture x
2.1. F-Tile Building Blocks 2.2. F-Tile Placement Rules 2.3. PMA Architecture 2.4. Clock Architecture
2.1. F-Tile Building Blocks x
2.1.1. FHT and FGT PMAs 2.1.2. 400G Hard IP and 200G Hard IP 2.1.3. PMA Data Rates 2.1.4. FEC Architecture 2.1.5. PCIe* Hard IP 2.1.6. Bonding Architecture 2.1.7. Deskew Logic 2.1.8. Embedded Multi-die Interconnect Bridge (EMIB) 2.1.9. IEEE 1588 Precision Time Protocol for Ethernet 2.1.10. Clock Networks 2.1.11. Reconfiguration Interfaces
2.2. F-Tile Placement Rules x
2.2.1. PMA-to-Fracture Mapping 2.2.2. Determining Which PMA to Map to Which Fracture 2.2.3. Hard IP Placement Rules 2.2.4. IEEE 1588 Precision Time Protocol Placement Rules 2.2.5. Topologies 2.2.6. FEC Placement Rules 2.2.7. Clock Rules and Restrictions 2.2.8. Bonding Placement Rules 2.2.9. Preserving Unused PMA Lanes
2.2.1. PMA-to-Fracture Mapping x
2.2.1.1. FHT-PMA-to-400G-Hard-IP-Fracture Mapping 2.2.1.2. FGT-PMA-to-400G-Hard-IP-Fracture Mapping 2.2.1.3. FGT-PMA-to-200G-Hard-IP-Fracture Mapping
2.2.2. Determining Which PMA to Map to Which Fracture x
2.2.2.1. Implementing One 200GbE-4 Interface with 400G Hard IP and FHT 2.2.2.2. Implementing One 200GbE-2 Interface with 400G Hard IP and FHT 2.2.2.3. Implementing One 100GbE-1 Interface with 400G Hard IP and FHT 2.2.2.4. Implementing One 100GbE-4 Interface with 400G Hard IP and FGT 2.2.2.5. Implementing One 10GbE-1 Interface with 200G Hard IP and FGT 2.2.2.6. Implementing Three 25GbE-1 Interfaces with 400G Hard IP and FHT 2.2.2.7. Implementing One 50GbE-1 and Two 25GbE-1 Interfaces with 400G Hard IP and FHT 2.2.2.8. Implementing One 100GbE-1 and Two 25GbE-1 Interfaces with 400G Hard IP and FHT 2.2.2.9. Implementing Two 100GbE-1 and One 25GbE-1 Interfaces with 400G Hard IP and FHT 2.2.2.10. Implementing 100GbE-1, 100GbE-2, and 50GbE-1 Interfaces with 400G Hard IP and FHT
2.2.5. Topologies x
2.2.5.1. Topology 5: 400G Hard IP (FHT) + 200G Hard IP (FGT) Example 2.2.5.2. Topology 6a: 400G Hard IP with Mixed Transceiver Mode Example 2.2.5.3. Topology 14: 1x PCIe x4 + 400G Hard IP (FGT) with PTP Example
2.2.8. Bonding Placement Rules x
2.2.8.1. Bonded Lanes Use Case 1 2.2.8.2. Bonded Lanes Use Case 2
2.3. PMA Architecture x
2.3.1. FHT PMA Architecture 2.3.2. FGT PMA Architecture
2.3.1. FHT PMA Architecture x
2.3.1.1. FHT Transmitter PMA Architecture 2.3.1.2. FHT Receiver PMA Architecture 2.3.1.3. FHT PMA Loopback Modes
2.3.1.1. FHT Transmitter PMA Architecture x
2.3.1.1.1. FHT Transmitter Buffer and Phase Generator 2.3.1.1.2. FHT Serializer 2.3.1.1.3. FHT Gray-Coder and Pre-Coder 2.3.1.1.4. FHT Data Pattern Generator and Verifier
2.3.1.2. FHT Receiver PMA Architecture x
2.3.1.2.1. FHT Receiver Buffer and Equalizer 2.3.1.2.2. CDR Block 2.3.1.2.3. FHT Deserializer
2.3.2. FGT PMA Architecture x
2.3.2.1. FGT Transmitter PMA Architecture 2.3.2.2. FGT Receiver PMA Architecture 2.3.2.3. FGT PMA Tuning 2.3.2.4. FGT PMA Loopback Modes
2.3.2.1. FGT Transmitter PMA Architecture x
2.3.2.1.1. FGT Transmitter Buffer and Phase Generator 2.3.2.1.2. FGT Serializer 2.3.2.1.3. FGT Gray-Coder and Pre-Coder 2.3.2.1.4. FGT Data Pattern Generator and Verifier
2.3.2.2. FGT Receiver PMA Architecture x
2.3.2.2.1. FGT Receiver Buffer and Equalizer 2.3.2.2.2. Control Unit 2.3.2.2.3. FGT Deserializer
2.4. Clock Architecture x
2.4.1. Reference Clock Network 2.4.2. Datapath Clock Network 2.4.3. System PLL 2.4.4. Datapath Clock Cadences
2.4.1. Reference Clock Network x
2.4.1.1. FHT Reference Clock Network 2.4.1.2. FGT and System PLL Reference Clock Network 2.4.1.3. FGT Primary PLL Configuration
2.4.1.2. FGT and System PLL Reference Clock Network x
2.4.1.2.1. FGT Reference Clock Receiver Analog Front End
3. Implementing the F-Tile PMA/FEC Direct PHY IP x
3.1. F-Tile PMA/FEC Direct PHY IP Overview 3.2. Designing with F-Tile PMA/FEC Direct PHY IP 3.3. Configuring the IP 3.4. Signal and Port Reference 3.5. Bit Mapping for PMA and FEC Mode PHY TX and RX Datapath 3.6. Clocking 3.7. Custom Cadence Generation Ports and Logic 3.8. Asserting Reset 3.9. Bonding Implementation 3.10. Independent Port Configurations 3.11. Configuration Registers 3.12. Configurable Quartus® Prime Software Settings 3.13. Configuring the F-Tile PMA/FEC Direct PHY IP for Hardware Testing 3.14. Hardware Configuration Using the Avalon® Memory-Mapped Interface
3.1. F-Tile PMA/FEC Direct PHY IP Overview x
3.1.1. PMA Direct Supported Modes 3.1.2. FEC Direct Supported Modes 3.1.3. Unsupported PMA/FEC Modes
3.2. Designing with F-Tile PMA/FEC Direct PHY IP x
3.2.1. Preset IP Parameter Settings
3.3. Configuring the IP x
3.3.1. General and Common Datapath Options 3.3.2. TX Datapath Options 3.3.3. RX Datapath Options 3.3.4. RS-FEC (Reed Solomon Forward Error Correction) Options 3.3.5. Avalon® Memory Mapped Interface Options 3.3.6. Register Map IP-XACT Support 3.3.7. Example Design Generation 3.3.8. Analog Parameter Options
3.3.1. General and Common Datapath Options x
3.3.1.1. FGT PMA Configuration Rules for SATA mode 3.3.1.2. FGT PMA Configuration Rules for GPON Mode
3.3.2. TX Datapath Options x
3.3.2.1. TX PMA interface Parameters
3.3.3. RX Datapath Options x
3.3.3.1. RX FGT PMA Interface Options
3.4. Signal and Port Reference x
3.4.1. TX and RX Parallel and Serial Interface Signals 3.4.2. TX and RX Reference Clock and Clock Output Interface Signals 3.4.3. Reset Signals 3.4.4. RS-FEC Signals 3.4.5. Custom Cadence Control and Status Signals 3.4.6. TX PMA Control Signals 3.4.7. RX PMA Status Signals 3.4.8. TX and RX PMA and Core Interface FIFO Signals 3.4.9. PMA Avalon® Memory Mapped Interface Signals 3.4.10. Datapath Avalon® Memory Mapped Interface Signals
3.4.10. Datapath Avalon® Memory Mapped Interface Signals x
3.4.10.1. Number of Datapath Memory Mapped Avalon® Interfaces and Additional Address Bits per Interface
3.5. Bit Mapping for PMA and FEC Mode PHY TX and RX Datapath x
3.5.1. Parallel Data Mapping Information 3.5.2. TX and RX Parallel Data Mapping Information for Different Configurations 3.5.3. Example of TX Parallel Data for PMA Width = 8, 10, 16, 20, 32 (X=1) 3.5.4. Example of TX Parallel Data for PMA width = 64 (X=2) 3.5.5. Example of TX Parallel Data for PMA width = 64 (X=2) for FEC Direct Mode
3.5.2. TX and RX Parallel Data Mapping Information for Different Configurations x
3.5.2.1. TX Parallel Data Mapping Information for SATA Protocol Mode for Different Configurations
3.6. Clocking x
3.6.1. Clock Ports 3.6.2. Recommended tx/rx_coreclkin Connection and tx/rx_clkout2 Source 3.6.3. Port Widths and Recommended Connections for tx/rx_coreclkin, tx/rx_clkout, and tx/rx_clkout2 3.6.4. FGT PMA Fractional Mode 3.6.5. FGT RX CDR Clock Output
3.6.5. FGT RX CDR Clock Output x
3.6.5.1. Dynamically Configure the FGT RX CDR Clock Output
3.7. Custom Cadence Generation Ports and Logic x
3.7.1. Enabling the tx_cadence_slow_clk_locked Port 3.7.2. Rate Match FIFO
3.8. Asserting Reset x
3.8.1. Reset Signal Requirements 3.8.2. Power On Reset Requirements 3.8.3. Reset Signals—Block Level 3.8.4. Reset Signals—Descriptions 3.8.5. Status Signals—Descriptions 3.8.6. Run-time Reset Sequence—TX 3.8.7. Run-time Reset Sequence—RX 3.8.8. Run-time Reset Sequence—TX + RX 3.8.9. Run-time Reset Sequence—TX with FEC
3.8.8. Run-time Reset Sequence—TX + RX x
3.8.8.1. Run-time Reset Sequence Approximate Time Durations
3.11. Configuration Registers x
3.11.1. PMA and FEC Direct PHY Soft CSR Register Map 3.11.2. FHT PMA Register Map 3.11.3. FGT PMA Register Map 3.11.4. FEC Register Map 3.11.5. Lane Offset Address 3.11.6. Accessing Configuration Registers
3.11.6. Accessing Configuration Registers x
3.11.6.1. Accessing PMA and FEC Direct PHY Soft CSR Registers 3.11.6.2. Accessing FHT PMA Registers 3.11.6.3. Accessing FGT PMA Registers
3.11.6.2. Accessing FHT PMA Registers x
3.11.6.2.1. FHT PMA Register Address Range 0x40000 to 0x48000 3.11.6.2.2. FHT PMA Register Address Range 0x60000 to 0xF0030 3.11.6.2.3. FHT PMA Register Address 0xFFFFC
3.11.6.3. Accessing FGT PMA Registers x
3.11.6.3.1. FGT PMA Register Address Range 0x40000 to 0x48000 3.11.6.3.2. FGT PMA Register Address Range 0x60000 to 0x62004 3.11.6.3.3. FGT PMA Register Address Range 0x9003C to 0xF0028 3.11.6.3.4. FGT PMA Register Address 0xFFFFC
3.12. Configurable Quartus® Prime Software Settings x
3.12.1. FHT PMA Settings 3.12.2. FGT PMA Settings
3.13. Configuring the F-Tile PMA/FEC Direct PHY IP for Hardware Testing x
3.13.1. Using Debug Endpoint Interface within the F-Tile PMA/FEC Direct PHY IP 3.13.2. Using JTAG to Avalon® Master Bridge IP
3.13.1. Using Debug Endpoint Interface within the F-Tile PMA/FEC Direct PHY IP x
3.13.1.1. RTL Connection Example for Debug Endpoint Avalon® Interface
3.13.2. Using JTAG to Avalon® Master Bridge IP x
3.13.2.1. RTL Connection Example for JTAG to Avalon® Master Bridge IP
3.14. Hardware Configuration Using the Avalon® Memory-Mapped Interface x
3.14.1. FHT PMA 3.14.2. FGT PMA
3.14.1. FHT PMA x
3.14.1.1. Enabling Loopback 3.14.1.2. Enabling the PRBS Generator and Verifier for ES Devices 3.14.1.3. Obtaining BER Values for Production Devices 3.14.1.4. TX Equalizer Settings 3.14.1.5. TX Error Injection 3.14.1.6. RX Reconvergence 3.14.1.7. Preserving Unused Lanes
3.14.2. FGT PMA x
3.14.2.1. Direct Register Method 3.14.2.2. FGT Attribute Access Method
3.14.2.1. Direct Register Method x
3.14.2.1.1. Direct Register Method Examples
3.14.2.2. FGT Attribute Access Method x
3.14.2.2.1. FGT Attribute Access Method Example 1 3.14.2.2.2. FGT Attribute Access Method Example 2 3.14.2.2.3. FGT Attribute Access Method Example 3
4. Implementing the F-Tile Reference and System PLL Clocks IP x
4.1. IP Parameters 4.2. IP Port List 4.3. Mode of System PLL - System PLL Reference Clock and Output Frequencies 4.4. Guidelines for F-Tile Reference and System PLL Clocks IP Usage 4.5. Guidelines for Refclk #i is Active At and After Device Configuration 4.6. Guidelines for Obtaining the Lock Status and Resetting the FGT and FHT TX PLLs
4.5. Guidelines for Refclk #i is Active At and After Device Configuration x
4.5.1. Guidelines for System PLL Reference Clock 4.5.2. Guidelines for FGT Reference Clock
4.6. Guidelines for Obtaining the Lock Status and Resetting the FGT and FHT TX PLLs x
4.6.1. How to Read the Real-Time Lock Status of the FGT TX PLL 4.6.2. How to Read the Real-Time Lock Status of the FHT Lane TX PLL 4.6.3. How to Read the Real-Time Lock Status of the FHT Common TX PLL 4.6.4. How to Reset the FGT TX PLL 4.6.5. How to Reset the FHT Lane TX PLL and Common PLL
4.6.1. How to Read the Real-Time Lock Status of the FGT TX PLL x
4.6.1.1. How to Determine the TX PLL Your FGT Channel is Using
4.6.3. How to Read the Real-Time Lock Status of the FHT Common TX PLL x
4.6.3.1. How to Determine Which Common PLL Your FHT Channel is Using
5. F-Tile PMA/FEC Direct PHY Design Implementation x
5.1. Implementing the F-Tile PMA/FEC Direct PHY Design 5.2. Instantiating the F-Tile PMA/FEC Direct PHY IP 5.3. Implementing a RS-FEC Direct Design in the F-Tile PMA/FEC Direct PHY IP 5.4. Instantiating the F-Tile Reference and System PLL Clocks IP 5.5. Enabling Custom Cadence Generation Ports and Logic 5.6. Connecting the F-Tile PMA/FEC Direct PHY Design IP 5.7. Simulating the F-Tile PMA/FEC Direct PHY Design 5.8. F-Tile Interface Planning 5.9. Compiling a F-Tile Design with VHDL Configuration File as the Top Level Module
5.2. Instantiating the F-Tile PMA/FEC Direct PHY IP x
5.2.1. Setting General and Common Datapath Options 5.2.2. Setting TX Datapath Options 5.2.3. Setting RX Datapath Options
5.7. Simulating the F-Tile PMA/FEC Direct PHY Design x
5.7.1. PAM4 Encoding Schemes in Simulation
5.8. F-Tile Interface Planning x
5.8.1. F-Tile Interface Planner Usage Example
6. Supported Tools x
6.1. F-Tile Channel Placement Tool 6.2. F-Tile PMA and FEC Direct Port Mapping Calculator 6.3. F-Tile Clocking and Datapath Tool 6.4. F-Tile FGT TX Equalizer Tool 6.5. F-Tile FHT TX Equalizer Tool
7. Debugging F-Tile Transceiver Links x
7.1. F-Tile Transceiver Toolkit GUI 7.2. F-Tile Transceiver Debugging Flow Walkthrough 7.3. Transceiver Toolkit Parameter Settings 7.4. Using F-Tile Multirate IPs with Transceiver Toolkit 7.5. Troubleshooting Common Errors 7.6. Transceiver Toolkit Scripts
7.1. F-Tile Transceiver Toolkit GUI x
7.1.1. Collection View
7.2. F-Tile Transceiver Debugging Flow Walkthrough x
7.2.1. Modifying the Design to Enable F-Tile Transceiver Debug 7.2.2. Programming the Design into an Altera FPGA 7.2.3. Loading the Design to the Transceiver Toolkit 7.2.4. Creating Transceiver Links 7.2.5. Running BER Tests 7.2.6. Running Eye Viewer Tests 7.2.7. Running Link Optimization Tests 7.2.8. Checking FEC Statistics 7.2.9. Vertical Bathtub Curve Measurements (VBCM) Data
7.3. Transceiver Toolkit Parameter Settings x
7.3.1. Dashboard
7.4. Using F-Tile Multirate IPs with Transceiver Toolkit x
7.4.1. F-Tile PMA/FEC Direct PHY Multirate IP 7.4.2. F-Tile Ethernet Multirate IP 7.4.3. Ethernet Subsystem FPGA IP
7.6. Transceiver Toolkit Scripts x
7.6.1. Supported Transceiver Toolkit Scripts 7.6.2. Modifying the Scripts 7.6.3. Script Execution 7.6.4. Example of the Results in Tcl Console
A. Appendix x
A.1. Agilex™ 7 F-Tile OPNs A.2. OSC_CLK_1 QSF Assignment Requirement A.3. FGT Internal Serial Loopback Sequence for RX Manual Tuning ( Quartus® Prime Pro Edition Software Versions Before 25.1.1) A.4. FGT Internal Serial Loopback Sequence for RX Manual Tuning ( Quartus® Prime Pro Edition Software Versions from 25.1.1 Onwards) A.5. Transceiver Toolkit Helper Script A.6. F-Tile Tuning Guidelines
A.5. Transceiver Toolkit Helper Script x
A.5.1. Introduction A.5.2. Executing the Script
A.6. F-Tile Tuning Guidelines x
A.6.1. Introduction A.6.2. Equalization Techniques Overview A.6.3. Equalization Recommendations for F-Tile FGT PMA Transceivers A.6.4. F-Tile FGT PMA Tuning Guide A.6.5. Equalization Recommendations for F-Tile FHT PMA Transceivers A.6.6. F-Tile FHT PMA Tuning Guide A.6.7. Appendix
A.6.1. Introduction x
A.6.1.1. F-Tile PMA Overview A.6.1.2. Equalization Techniques Overview
A.6.1.2. Equalization Techniques Overview x
A.6.1.2.1. FGT Transmitter Equalization Tuning Taps A.6.1.2.2. FGT Receiver Adaptation A.6.1.2.3. FGT Media Selection A.6.1.2.4. FHT Transmitter Equalization Tuning Taps
A.6.3. Equalization Recommendations for F-Tile FGT PMA Transceivers x
A.6.3.1. F-Tile FGT Transmitter Equalization Parameters A.6.3.2. F-Tile FGT Transmitter Setting Recommendations A.6.3.3. F-Tile FGT Receiver Equalization Parameters A.6.3.4. F-Tile FGT Receiver Setting Recommendations
A.6.4. F-Tile FGT PMA Tuning Guide x
A.6.4.1. F-Tile FGT NRZ Tuning Flow A.6.4.2. F-Tile FGT Hardware Setup A.6.4.3. F-Tile FGT Tuning Examples
A.6.4.3. F-Tile FGT Tuning Examples x
A.6.4.3.1. Example 1 : F-Tile FGT 25 Gbps NRZ Design A.6.4.3.2. Example 2 : F-Tile FGT 58 Gbps PAM4 and FEC Design A.6.4.3.3. Example 3 : F-Tile FGT 5 Gbps NRZ Design
A.6.5. Equalization Recommendations for F-Tile FHT PMA Transceivers x
A.6.5.1. F-Tile FHT Transmitter Equalization Parameters A.6.5.2. F-Tile FHT Transmitter Setting Recommendations A.6.5.3. F-Tile FHT Receiver Equalization Parameters
A.6.6. F-Tile FHT PMA Tuning Guide x
A.6.6.1. F-Tile FHT Tuning Flow A.6.6.2. F-Tile FHT Hardware Setup A.6.6.3. F-Tile FHT Tuning Examples
A.6.6.3. F-Tile FHT Tuning Examples x
A.6.6.3.1. Example 1 : F-Tile FHT 106 Gbps PAM4 Design (Short Reach) A.6.6.3.2. Example 2 : F-Tile FHT 106 Gbps PAM4 Design (Long Reach) A.6.6.3.3. Example 3 : F-Tile FHT 25 Gbps NRZ Design (Short Reach) A.6.6.3.4. Example 4 : F-Tile FHT 50 Gbps PAM4 Design (Short Reach) A.6.6.3.5. Example 5 : F-Tile FHT 106 Gbps PAM4 Design (Short Reach) A.6.6.3.6. Example 6 : F-Tile FHT 106 Gbps PAM4 Design (Long Reach) A.6.6.3.7. Example 7 : F-Tile FHT 25 Gbps NRZ Design (Short Reach) A.6.6.3.8. Example 8 : F-Tile FHT 25 Gbps NRZ Design (Long Reach) A.6.6.3.9. Example 9 : F-Tile FHT 50 Gbps PAM4 Design (Short Reach) A.6.6.3.10. Example 10 : F-Tile FHT 50 Gbps PAM4 Design (Long Reach)
A.6.7. Appendix x
A.6.7.1. FCI Backplane Design A.6.7.2. F-Tile FGT Tuning Script A.6.7.3. F-Tile FGT Attribute Access Sequence
1. F-Tile Overview
2. F-Tile Architecture
3. Implementing the F-Tile PMA/FEC Direct PHY IP
4. Implementing the F-Tile Reference and System PLL Clocks IP
5. F-Tile PMA/FEC Direct PHY Design Implementation
6. Supported Tools
7. Debugging F-Tile Transceiver Links
8. F-Tile Architecture and PMA and FEC Direct PHY IP User Guide Archives
9. Document Revision History for the F-Tile Architecture and PMA and FEC Direct PHY IP User Guide
A. Appendix

4.2. IP Port List

The following table lists the ports for the IP; all ports are 1-bit wide.

Table 101.   F-Tile Reference and System PLL Clocks IP Port ListRefer to Port Connection Guidelines between F-Tile Reference and System PLL Clocks IP and F-Tile PMA/FEC Direct PHY IP for recommended connections.
Port Name Direction Description
FHT
in_refclk_fht_i Input FHT reference clock input port. Must and can only be mapped to the device reference clock pin. Maximum of 2 (i = 0 to 1) ports of this type.
out_fht_cmmpll_clk_i Output FHT common PLL output port. Must and can only be connected to protocol IPs, connected to FHT building-block. There can be a maximum of 2(i = 0 to 1) ports of this type.
FGT and System PLL
in_refclk_fgt_i Input FGT and system PLL reference clock input port. Must and can only be mapped to the device reference clock pin. This reference clock port can be connected to FGT PMA, system PLL or both. There can be a maximum of 10 (i = 0 to 9) ports of this type.
avmm_clk Input
Avalon® memory-mapped interface clock. This port is only available when at least one of Refclk #i is active at and after device configuration is set as Off. Altera recommends 100 to 250 MHz for this clock.
Note: Starting with Quartus® Prime Pro Edition software version 24.2, this port no longer functions and serves as a dummy port for backward compatibility.
avmm_reset Input
Avalon® memory-mapped interface reset. This port is only available when at least one of Refclk #i is active at and after device configuration is set as Off.
Note: Starting with Quartus® Prime Pro Edition software version 24.2, this port no longer functions and serves as a dummy port for backward compatibility.
FGT
out_refclk_fgt_i Output FGT Refclk output port. Must and can only be connected to protocol IPs, connected to FGT building-block. There can be a maximum of 10 (i = 0 to 9) ports of this type.
Note: This signal cannot feed user logic.
en_refclk_fgt_i Input
FGT reference clock status control signal. This port is only available when the corresponding Refclk #i is active at and after device configuration set as Off. There can be a maximum of 10 (i = 0 to 9) ports of this type.
  • 1'b0 -> 1'b1: Low to high transition enables Refclk #i
  • 1'b1 -> 1'b0: High to low transition disables Refclk #i
Note: When you use the Refclk #i only for the system PLL and do not share it with the FGT PMA, you must still drive this port according to the above requirements to get the system PLL to function correctly.
disable_refclk_monitor_i Input
FGT reference clock monitor control signal. This port is only available when the corresponding Refclk #i is used by the FGT PMA or the system PLL. There can be a maximum of 10 (i = 0 to 9) ports of this type.
  • 1'b0: Enable Refclk #i monitor and protection circuit.
  • 1'b1: Disable Refclk #i monitor and protection circuit.
Altera recommends that you always enable the monitor and protection circuit by either driving this port to 1'b0 or leaving it unconnected.
This port is used for applications where the reference clock frequency is subject to change, for example, HDMI, SDI, OTN, and so on. The monitor and protection circuit may incorrectly detect the reference clock as inactive ​when its frequency is changing.
  • For HDMI application. you should drive this port according to F-Tile HDMI IP Design Example User Guide.
  • For other applications:
    • By default, you should drive this port to 1'b0.
    • Whenever you are going to change the reference clock frequency, you should drive this port to 1'b1 before the frequency change starts ​and drive this port to 1'b0 after frequency change is done.
When the Refclk #i becomes inactive, to prevent the FGT PMA lane performance from degradation:
  • If the monitor is enabled, a protection circuit acts automatically.
  • If the monitor is disabled, you have to control the en_refclk_fgt_i to perform high to low (1'b1 -> 1'b0) transition.
refclk_fgt_enabled_i Output

FGT reference clock status signal. This port is only available when the corresponding Refclk #i is active at and after device configuration is set to Off. There can be a maximum of 10 (i = 0 to 9) ports of this type. After you assert the en_refclk_fgt_i signal, this port indicates the presence of a reference clock on the device pins.

  • 1'b0: Indicates Refclk #i is not present at the device pins
  • 1'b1: Indicates Refclk #i is present at the device pins
This signal has valid outputs only when Refclk #i monitor is enabled.
Note: When you use the Refclk #i only for the system PLL and do not share it with the FGT PMA, you must still monitor this port to make sure that the system PLL functions correctly.
in_cdrclk_i Input Input port for FGT reference clock configured as CDR output. This port must and can only be connected to the protocol IP output CDR port. There can be a maximum of 2 (i = 0 to 1) ports of this type.
out_cdrclk_i Output Output port for FGT reference clock configured as CDR output. This port must and can only be connected to one of two FGT reference clock pins that can be configured as CDR outputs. You must specify the location assignment in the Quartus® Prime Pro Edition software qsf settings file for correct functionality. There can be a maximum of 2 (i = 0 to 1) ports of this type.
out_coreclk_i Output
FGT reference clock output port for user logic. This port is only available when the corresponding Export Refclk #i for use in user logic is set to On.
Note: This signal cannot directly feed the reference clock of the IOPLL IP.
System PLL
out_systempll_clk_i Output Output port of system PLL. This port must and can only be connected to system PLL clock input of protocol IP. There can be a maximum of 3 (i = 0 to 2) ports of this type.
out_systempll_synthlock_i Output System PLL lock status port which indicates if system PLL is locked to incoming reference clock. There can be a maximum of 3 (i = 0 to 2) ports of this type. You can use this port as a status or debug signal.
refclock_ready [2:0] Input
System PLL reference clock status control signal. This port is only available when all the enabled system PLL's corresponding Refclk #i is active at and after device configuration are set as Off.
  • bit[0] is used to control system PLL #0 reference clock.
  • bit[1] is used to control system PLL #1 reference clock.
  • bit[2] is used to control system PLL #2 reference clock.

When system PLL #i is disabled, bit[i] can be any value and does not matter. When system PLL #i is enabled, after the reference clock is available, you must assert bit[i] to notify the system PLL to start locking to the incoming reference clock.
refclock_status Output
System PLL reference clock status signal. This port is only available when all the enabled system PLL's corresponding Refclk #i is active at and after device configuration are set to Off. After you assert the refclock_ready signal, this port indicates the presence of a reference clock on the device pins.
  • 1'b0: The reference clock is not present at the device pins.
  • 1'b1: The reference clock is present at the device pins.
You can also use the out_systempll_synthlock_i signal to check the system PLL lock status.
Level Two Title