F-Tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 11/04/2024
Public
Document Table of Contents

3.11.6. Accessing Configuration Registers

This section summarizes how to access the configuration registers listed in the F-Tile PMA/FEC Direct PHY Intel® FPGA IP register map. You can use the detailed information to access the PMA and FEC Direct PHY Soft CSR registers, FHT PMA registers, and FGT PMA registers.

You must handle the conversion of byte addressing format to word addressing format by shifting the reconfiguration address bus by two bits when you access the configuration registers due to:
  • The registers listed in F-Tile PMA/FEC Direct PHY Intel® FPGA IP Register Map use byte addressing format.
  • F-Tile PMA/FEC Direct PHY Intel® FPGA IP uses word addressing format.
The following table summarizes how to calculate the register address for a N-channel design.
  • Lane ID is the physical location where the channel is placed at and corresponds to FGT/FHT0, 1, 2, and 3. For example, Lane 0 refers to FGT0/FHT0 and Lane3 refers to FGT3/FHT3.
  • Channel ID is the logical number of the PMA lanes, which corresponds to tx/rx_serial[0], [1], [2], up to [N-1]. For example, Channel 0 refers to tx/rx_serial[0] and Channel 3 refers to tx/rx_serial[3].
Note: If you enable the Enable separate Avalon® interface per fracture parameter, then each channel has its own Avalon® interface, and all Channel IDs are 0.
Table 90.  Register Map Address Calculation
Register Type Reconfiguration Interface Address Range Address Calculation
PMA_and_FEC_Direct_PHY_Soft_CSR reconfig_pdp 0x800 - 0x9F0 Address
FHT reconfig_xcvr 0x40000 - 0x48000 Address + 0x8000*Lane ID
0x60000 - 0xF0030 Address
0xFFFFC Address + 0x100000*Channel ID
FGT reconfig_xcvr 0x40000 - 0x48000 Address + 0x400000*integer(Channel ID/4) + 0x8000*Lane ID
0x62000 - 0x62004 Address + 0x400000*integer(Channel ID/4) + 0x4000*Lane ID
0x9003C - 0xF0028 Address + 0x400000*integer(Channel ID/4)
0xFFFFC Address + 0x100000*Channel ID
In order to access all the configuration registers, it is recommended that you set the Avalon® Memory-Mapped Interface as shown in the following figure.
Figure 94. Recommended Avalon Memory-Mapped Interface Settings