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Ixiasoft
Visible to Intel only — GUID: voi1654546052531
Ixiasoft
4.5. Guidelines to Indicate all System PLL Reference Clocks are Ready
When the system PLL #N (N = 0, 1, 2) mode is enabled but the reference clock is not available or stable at device programming time, you must set the Refclk is available at power-on parameter to Off. When the system PLL #N (N = 0, 1, 2) mode is disabled, you can ignore the reference clock.
For all enabled system PLLs that have the parameter Refclk is available at power-on set to On, you must provide stable reference clocks for the system PLLs at device programming time.
For all enabled system PLLs that have the parameter Refclk is available at power-on set to Off, system PLL does not start locking until you perform the Global Avalon® memory-mapped interface write operations signaling that all reference clocks are ready.