Quartus® Prime Pro Edition User Guide: Third-party Simulation

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ID 683870
Date 9/29/2025
Public
Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. FPGA Simulation Basics 2. Siemens EDA QuestaSim* Simulator Support 3. Synopsys VCS* Support 4. Aldec Active-HDL and Riviera-PRO Support 5. Cadence Xcelium* Parallel Simulator Support 6. Quartus® Prime Pro Edition User Guide Third-party Simulation Archive A. Quartus® Prime Pro Edition User Guides
1. FPGA Simulation Basics x
1.1. FPGA Simulation Essential Elements 1.2. Overview of Simulation Tool Flow 1.3. Simulation Tool Flow 1.4. Supported Simulation Flows 1.5. Supported Hardware Description Languages 1.6. Supported Simulation Types 1.7. Supported Simulators 1.8. Post-Fit Simulation Support by FPGA Family 1.9. Automating Simulation with the Run Simulation Feature 1.10. Using Precompiled Simulation Libraries 1.11. Enabling Fast Simulation Models for Agilex™ Devices 1.12. FPGA Simulation Basics Revision History
1.2. Overview of Simulation Tool Flow x
1.2.1. Compilation Stage 1.2.2. Elaboration Stage 1.2.3. Simulation Stage
1.3. Simulation Tool Flow x
1.3.1. Specifying Logical Libraries 1.3.2. Compiling Files Into Library Directories 1.3.3. The Quartus® Prime Simulation Library 1.3.4. Understanding Elaboration 1.3.5. Commands To Configure and Run Simulation 1.3.6. FPGA Simulation Generic Workflow
1.3.1. Specifying Logical Libraries x
1.3.1.1. Why Do We Need Logical Library Names?
1.3.2. Compiling Files Into Library Directories x
1.3.2.1. Inputs to Compilation Commands 1.3.2.2. Order of Files for Compilation Commands 1.3.2.3. Compilation Command Line Options 1.3.2.4. Module Definitions in Library Directories
1.3.3. The Quartus® Prime Simulation Library x
1.3.3.1. The Quartus® Prime Simulation Library Compiler 1.3.3.2. Running the Simulation Library Compiler in a Terminal 1.3.3.3. Running the Simulation Library Compiler in the GUI 1.3.3.4. Finding Logical Library Names in Simulation Library Compiler Output
1.3.4. Understanding Elaboration x
1.3.4.1. Elaboration Binding Phase 1.3.4.2. Elaboration Checks 1.3.4.3. Elaboration Options
1.9. Automating Simulation with the Run Simulation Feature x
1.9.1. Setting Up the Run Simulation Feature 1.9.2. Starting RTL Simulation from the Quartus® Prime GUI 1.9.3. Run RTL Simulation using Run Simulation in Batch Mode (Command-Line) 1.9.4. Simulating Example Designs using the Run Simulation Feature
1.9.1. Setting Up the Run Simulation Feature x
1.9.1.1. Installation Paths for Supported EDA Simulators (EDA Tool Options Page) 1.9.1.2. Simulation Flow Settings (EDA Tool Settings Page) 1.9.1.3. More EDA Netlist Writer Settings (EDA Tool Settings Page)
1.9.3. Run RTL Simulation using Run Simulation in Batch Mode (Command-Line) x
1.9.3.1. Specifying Required Simulation Settings for Run Simulation (Batch Mode) 1.9.3.2. Optional Simulation Settings for Run Simulation (Batch Mode) 1.9.3.3. Launching Simulation with the Run Simulation Feature 1.9.3.4. Running RTL Simulation using Run Simulation 1.9.3.5. Output Directories and Files for Run Simulation
1.10. Using Precompiled Simulation Libraries x
1.10.1. Enabling Precompiled Simulation Libraries 1.10.2. Implementing Precompiled Simulation Libraries
2. Siemens EDA QuestaSim* Simulator Support x
2.1. Quick Start Example (QuestaSim* with Verilog) 2.2. QuestaSim* Simulator Guidelines 2.3. Using the Qrun Flow 2.4. QuestaSim* Simulation Setup Script Example 2.5. Sourcing QuestaSim* Simulator Setup Scripts 2.6. Unsupported Features 2.7. Siemens EDA QuestaSim* Simulator Support Revision History
2.2. QuestaSim* Simulator Guidelines x
2.2.1. Passing Parameter Information from Verilog HDL to VHDL 2.2.2. Viewing Simulation Messages 2.2.3. Generating Signal Activity Data for Power Analysis 2.2.4. Viewing Simulation Waveforms
2.3. Using the Qrun Flow x
2.3.1. Specifying Simulation File Generation Settings 2.3.2. Generating the Simulation Model and Setup Scripts 2.3.3. Generating the Testbench System 2.3.4. Generating Example Design Simulation Files 2.3.5. Recommendations for Using Qrun
3. Synopsys VCS* Support x
3.1. Quick Start Example (VCS with Verilog) 3.2. VCS Guidelines 3.3. VCS Simulation Setup Script Example 3.4. Sourcing Synopsys VCS* (3-Step) Simulator Setup Scripts 3.5. Sourcing Synopsys VCS* (2-Step) Simulator Setup Scripts 3.6. Synopsys VCS* and VCS MX Support Revision History
4. Aldec Active-HDL and Riviera-PRO Support x
4.1. Quick Start Example (Active-HDL VHDL) 4.2. Aldec Active-HDL and Riviera-PRO Guidelines 4.3. Using Simulation Setup Scripts 4.4. Sourcing Aldec ActiveHDL* or Riviera Pro* Simulator Setup Scripts 4.5. Aldec Active-HDL* and Riviera-PRO * Support Revision History
5. Cadence Xcelium* Parallel Simulator Support x
5.1. Using the Command-Line Interface 5.2. Generating Simulator Setup Script Templates 5.3. Sourcing Cadence Xcelium* Simulator Setup Scripts 5.4. Cadence Xcelium* Parallel Simulator Support Revision History
Answers to Top FAQs
1. FPGA Simulation Basics
2. Siemens EDA QuestaSim* Simulator Support
3. Synopsys VCS* Support
4. Aldec Active-HDL and Riviera-PRO Support
5. Cadence Xcelium* Parallel Simulator Support
6. Quartus® Prime Pro Edition User Guide Third-party Simulation Archive
A. Quartus® Prime Pro Edition User Guides

1.9.1. Setting Up the Run Simulation Feature

You must first setup the Run Simulation feature before using it to automate portions of the simulation flow.

To setup the Run Simulation feature by specifying the settings that identify your simulator, output path, and other options, follow these steps:

  1. Open a project in the Quartus® Prime software.
  2. Click Tools > Options > EDA Tool Options and specify the location of your simulator executable file, as Execution Paths for Supported EDA Simulators describes in detail.
    Figure 7. Specifying Simulator Install Path


  3. To enable automated generation of the IP simulation models whenever you generate HDL for IP in Platform Designer, click Tools > Options > Board and IP Settings > IP Simulation. Make sure Generate IP simulation model when generating IP option is turned on.
    Figure 8. Specifying Automated IP Simulation Model Generation


  4. Click Assignments > Settings > EDA Tool Settings > Simulation and specify the following simulation settings in the Simulation pane:
    Figure 9. Simulation pane of the EDA Tool Settings dialog
    1. Set the general simulation settings:
      Table 8.  Simulation Options (EDA Tool Settings Page) Options Dialog Box
      Option Allowed Values Description
      Tool name
      • <None>5
      • Riviera-PRO
      • QuestaSim
      • Questa Altera FPGA
      • VCS (2-step, to be deprecated)4
      • VCS (3-step)
      • Xcelium
      • Custom
      		 Specifies the supported simulator to automatically run.
      Format for output netlist
      • Verilog HDL
      • VHDL
      		 Specifies Verilog or VHDL as the format for the output netlist.

      The setting does not apply to RTL simulation.
      Output directory Any valid path. Specifies the directory to store all output files for simulation.

      The default path is simulation/<simulator> .
      Map illegal HDL characters
      • Disabled (default)
      • Enabled

      When enabled, this option directs the EDA Netlist Writer to map illegal characters for VHDL or Verilog HDL. The setting does not apply to RTL simulation.

      If you select VHDL for Format for output netlist, the EDA Netlist writer maps non-alphanumeric characters, including brackets ([]), parentheses, (()), angle brackets (<>), and braces ({}) to (_a) in VHDL Output Files. This option generates VHDL 1987 compatible names.

      If you select Verilog HDL for Format for output netlist, the EDA Netlist writer maps the vertical bar (|), tilde (~), and colon (:) characters in hierarchical node names to the legal Verilog HDL characters z, x, and underscore (_) in Verilog Output Files. This option also maps other illegal non-alphanumeric characters, including brackets ([]), parentheses, (()), angle brackets (<>), and braces ({}) to underscore (_).
    2. For Testbench Specification, click New and enter the testbench information, including the Top level module in testbench, Simulation period, and Testbench and simulation files options.
      Figure 10. Defining Testbench Specification


    3. Click More EDA Netlist Writer Settings to specify settings that control how the Compiler generates and formates the gate-level netlist for gate-level simulation.
      Figure 11. More EDA Netlist Writer Settings Dialog Box
    4. Click Simulation Flow Settings to specify additional options for the automated simulation flow, as Simulation Flow Settings describes in detail.
      Figure 12. Simulation Flow Settings Dialog Box



Section Content
Installation Paths for Supported EDA Simulators (EDA Tool Options Page)
Simulation Flow Settings (EDA Tool Settings Page)
More EDA Netlist Writer Settings (EDA Tool Settings Page)

4 Starting in version 25.1, the "VCS MX" tool flow is now referred to as the "VCS (3-step) flow" which is fully supported. The “VCS” tool flow is now referred to as “VCS (2-step) flow" which is also supported but is deprecated.
5 Not supported by Run Simulation
Level Two Title