Quartus® Prime Pro Edition User Guide: Third-party Simulation

Download PDF
ID 683870
Date 9/29/2025
Public
Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. FPGA Simulation Basics 2. Siemens EDA QuestaSim* Simulator Support 3. Synopsys VCS* Support 4. Aldec Active-HDL and Riviera-PRO Support 5. Cadence Xcelium* Parallel Simulator Support 6. Quartus® Prime Pro Edition User Guide Third-party Simulation Archive A. Quartus® Prime Pro Edition User Guides
1. FPGA Simulation Basics x
1.1. FPGA Simulation Essential Elements 1.2. Overview of Simulation Tool Flow 1.3. Simulation Tool Flow 1.4. Supported Simulation Flows 1.5. Supported Hardware Description Languages 1.6. Supported Simulation Types 1.7. Supported Simulators 1.8. Post-Fit Simulation Support by FPGA Family 1.9. Automating Simulation with the Run Simulation Feature 1.10. Using Precompiled Simulation Libraries 1.11. Enabling Fast Simulation Models for Agilex™ Devices 1.12. FPGA Simulation Basics Revision History
1.2. Overview of Simulation Tool Flow x
1.2.1. Compilation Stage 1.2.2. Elaboration Stage 1.2.3. Simulation Stage
1.3. Simulation Tool Flow x
1.3.1. Specifying Logical Libraries 1.3.2. Compiling Files Into Library Directories 1.3.3. The Quartus® Prime Simulation Library 1.3.4. Understanding Elaboration 1.3.5. Commands To Configure and Run Simulation 1.3.6. FPGA Simulation Generic Workflow
1.3.1. Specifying Logical Libraries x
1.3.1.1. Why Do We Need Logical Library Names?
1.3.2. Compiling Files Into Library Directories x
1.3.2.1. Inputs to Compilation Commands 1.3.2.2. Order of Files for Compilation Commands 1.3.2.3. Compilation Command Line Options 1.3.2.4. Module Definitions in Library Directories
1.3.3. The Quartus® Prime Simulation Library x
1.3.3.1. The Quartus® Prime Simulation Library Compiler 1.3.3.2. Running the Simulation Library Compiler in a Terminal 1.3.3.3. Running the Simulation Library Compiler in the GUI 1.3.3.4. Finding Logical Library Names in Simulation Library Compiler Output
1.3.4. Understanding Elaboration x
1.3.4.1. Elaboration Binding Phase 1.3.4.2. Elaboration Checks 1.3.4.3. Elaboration Options
1.9. Automating Simulation with the Run Simulation Feature x
1.9.1. Setting Up the Run Simulation Feature 1.9.2. Starting RTL Simulation from the Quartus® Prime GUI 1.9.3. Run RTL Simulation using Run Simulation in Batch Mode (Command-Line) 1.9.4. Simulating Example Designs using the Run Simulation Feature
1.9.1. Setting Up the Run Simulation Feature x
1.9.1.1. Installation Paths for Supported EDA Simulators (EDA Tool Options Page) 1.9.1.2. Simulation Flow Settings (EDA Tool Settings Page) 1.9.1.3. More EDA Netlist Writer Settings (EDA Tool Settings Page)
1.9.3. Run RTL Simulation using Run Simulation in Batch Mode (Command-Line) x
1.9.3.1. Specifying Required Simulation Settings for Run Simulation (Batch Mode) 1.9.3.2. Optional Simulation Settings for Run Simulation (Batch Mode) 1.9.3.3. Launching Simulation with the Run Simulation Feature 1.9.3.4. Running RTL Simulation using Run Simulation 1.9.3.5. Output Directories and Files for Run Simulation
1.10. Using Precompiled Simulation Libraries x
1.10.1. Enabling Precompiled Simulation Libraries 1.10.2. Implementing Precompiled Simulation Libraries
2. Siemens EDA QuestaSim* Simulator Support x
2.1. Quick Start Example (QuestaSim* with Verilog) 2.2. QuestaSim* Simulator Guidelines 2.3. Using the Qrun Flow 2.4. QuestaSim* Simulation Setup Script Example 2.5. Sourcing QuestaSim* Simulator Setup Scripts 2.6. Unsupported Features 2.7. Siemens EDA QuestaSim* Simulator Support Revision History
2.2. QuestaSim* Simulator Guidelines x
2.2.1. Passing Parameter Information from Verilog HDL to VHDL 2.2.2. Viewing Simulation Messages 2.2.3. Generating Signal Activity Data for Power Analysis 2.2.4. Viewing Simulation Waveforms
2.3. Using the Qrun Flow x
2.3.1. Specifying Simulation File Generation Settings 2.3.2. Generating the Simulation Model and Setup Scripts 2.3.3. Generating the Testbench System 2.3.4. Generating Example Design Simulation Files 2.3.5. Recommendations for Using Qrun
3. Synopsys VCS* Support x
3.1. Quick Start Example (VCS with Verilog) 3.2. VCS Guidelines 3.3. VCS Simulation Setup Script Example 3.4. Sourcing Synopsys VCS* (3-Step) Simulator Setup Scripts 3.5. Sourcing Synopsys VCS* (2-Step) Simulator Setup Scripts 3.6. Synopsys VCS* and VCS MX Support Revision History
4. Aldec Active-HDL and Riviera-PRO Support x
4.1. Quick Start Example (Active-HDL VHDL) 4.2. Aldec Active-HDL and Riviera-PRO Guidelines 4.3. Using Simulation Setup Scripts 4.4. Sourcing Aldec ActiveHDL* or Riviera Pro* Simulator Setup Scripts 4.5. Aldec Active-HDL* and Riviera-PRO * Support Revision History
5. Cadence Xcelium* Parallel Simulator Support x
5.1. Using the Command-Line Interface 5.2. Generating Simulator Setup Script Templates 5.3. Sourcing Cadence Xcelium* Simulator Setup Scripts 5.4. Cadence Xcelium* Parallel Simulator Support Revision History
Answers to Top FAQs
1. FPGA Simulation Basics
2. Siemens EDA QuestaSim* Simulator Support
3. Synopsys VCS* Support
4. Aldec Active-HDL and Riviera-PRO Support
5. Cadence Xcelium* Parallel Simulator Support
6. Quartus® Prime Pro Edition User Guide Third-party Simulation Archive
A. Quartus® Prime Pro Edition User Guides

1.11. Enabling Fast Simulation Models for Agilex™ Devices

For the Agilex™ portfolio of FPGA devices, the default simulation model for IP example designs is a fast simulation model that offers improved simulation time.
Restriction: Fast simulation models are not available for the following IPs:
  • R-Tile for Compute Express Link (CXL) Solution

  • AXI Multichannel DMA IP for PCI Express

  • DisplayPort IP

To enable the fast simulation models:
  1. Generate the example design from the .ip file or create a custom design for simulation.
  2. Update the auto-generated simulation script to point to Fast Simulation Models in Agilex™ 3, Agilex™ 5, or Agilex™ 7 FPGA designs by setting the simulation environment variables as follows:
    • For Siemens EDA QuestaSim* simulators, update the Tcl-based scripts (msim_setup.tcl) with the following variables:
      set DEVICES_SIM_LIB_DIR "$QUARTUS_INSTALL_DIR/../devices/sim_lib2/"
set QUARTUS_SIM_LIB_DIR "$QUARTUS_INSTALL_DIR/eda/sim_lib2/
    • For Synopsys VCS* simluators, udate the Platform Designer-generated script (vcs_setup.sh or vcsmx_setup.sh) with the following variables:
      DEVICES_SIM_LIB_DIR="$QUARTUS_INSTALL_DIR/../devices/sim_lib2/"
QUARTUS_SIM_LIB_DIR="$QUARTUS_INSTALL_DIR/eda/sim_lib2/
  3. Update the auto-generated simulation scripts to remove commands or options that slow down the simulation as follows:
    • For Siemens EDA QuestaSim* simulators, make the following updates:
      • In the top-level example design simulation script, ensure ld and elab are called (instead of ld_debug and elab_debug).
      • If present, remove -voptargs=+acc under elab_debug in mentor/msim_setup.tcl.
      • If present, remove -voptargs=+acc under proc get_elab_options in common/modelsim_files.tcl.
      • Remove commands that dump out waveforms and other commands or options that can slow down the simulation.
    • For Synopsys VCS* simluators, make the following updates:
      • Remove any debug elaboration options in the top-level script ( start with -debug_).
      • Remove the -kdb option and any elaboration and simulation options to dump waveforms (such as +fsdb or +vpd dumps).

Revert to Default Simulation Models

To revert to the default simulation models from the fast simulation models:
  1. Generate the example design from the .ip file or create a custom design for simulation.
  2. Update the auto-generated simulation scripts by setting the simulation environment variables as follows:
    • For Siemens EDA QuestaSim* simulators, update the Tcl-based scripts (msim_setup.tcl) with the following variables:
      set DEVICES_SIM_LIB_DIR "$QUARTUS_INSTALL_DIR/../devices/sim_lib/"
set QUARTUS_SIM_LIB_DIR "$QUARTUS_INSTALL_DIR/eda/sim_lib/
    • For Synopsys VCS* simluators, udate the Platform Designer-generated script (vcs_setup.sh or vcsmx_setup.sh) with the following variables:
      DEVICES_SIM_LIB_DIR="$QUARTUS_INSTALL_DIR/../devices/sim_lib/"
QUARTUS_SIM_LIB_DIR="$QUARTUS_INSTALL_DIR/eda/sim_lib/
Level Two Title