Quartus® Prime Pro Edition User Guide: Third-party Simulation

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ID 683870
Date 9/29/2025
Public
Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. FPGA Simulation Basics 2. Siemens EDA QuestaSim* Simulator Support 3. Synopsys VCS* Support 4. Aldec Active-HDL and Riviera-PRO Support 5. Cadence Xcelium* Parallel Simulator Support 6. Quartus® Prime Pro Edition User Guide Third-party Simulation Archive A. Quartus® Prime Pro Edition User Guides
1. FPGA Simulation Basics x
1.1. FPGA Simulation Essential Elements 1.2. Overview of Simulation Tool Flow 1.3. Simulation Tool Flow 1.4. Supported Simulation Flows 1.5. Supported Hardware Description Languages 1.6. Supported Simulation Types 1.7. Supported Simulators 1.8. Post-Fit Simulation Support by FPGA Family 1.9. Automating Simulation with the Run Simulation Feature 1.10. Using Precompiled Simulation Libraries 1.11. Enabling Fast Simulation Models for Agilex™ Devices 1.12. FPGA Simulation Basics Revision History
1.2. Overview of Simulation Tool Flow x
1.2.1. Compilation Stage 1.2.2. Elaboration Stage 1.2.3. Simulation Stage
1.3. Simulation Tool Flow x
1.3.1. Specifying Logical Libraries 1.3.2. Compiling Files Into Library Directories 1.3.3. The Quartus® Prime Simulation Library 1.3.4. Understanding Elaboration 1.3.5. Commands To Configure and Run Simulation 1.3.6. FPGA Simulation Generic Workflow
1.3.1. Specifying Logical Libraries x
1.3.1.1. Why Do We Need Logical Library Names?
1.3.2. Compiling Files Into Library Directories x
1.3.2.1. Inputs to Compilation Commands 1.3.2.2. Order of Files for Compilation Commands 1.3.2.3. Compilation Command Line Options 1.3.2.4. Module Definitions in Library Directories
1.3.3. The Quartus® Prime Simulation Library x
1.3.3.1. The Quartus® Prime Simulation Library Compiler 1.3.3.2. Running the Simulation Library Compiler in a Terminal 1.3.3.3. Running the Simulation Library Compiler in the GUI 1.3.3.4. Finding Logical Library Names in Simulation Library Compiler Output
1.3.4. Understanding Elaboration x
1.3.4.1. Elaboration Binding Phase 1.3.4.2. Elaboration Checks 1.3.4.3. Elaboration Options
1.9. Automating Simulation with the Run Simulation Feature x
1.9.1. Setting Up the Run Simulation Feature 1.9.2. Starting RTL Simulation from the Quartus® Prime GUI 1.9.3. Run RTL Simulation using Run Simulation in Batch Mode (Command-Line) 1.9.4. Simulating Example Designs using the Run Simulation Feature
1.9.1. Setting Up the Run Simulation Feature x
1.9.1.1. Installation Paths for Supported EDA Simulators (EDA Tool Options Page) 1.9.1.2. Simulation Flow Settings (EDA Tool Settings Page) 1.9.1.3. More EDA Netlist Writer Settings (EDA Tool Settings Page)
1.9.3. Run RTL Simulation using Run Simulation in Batch Mode (Command-Line) x
1.9.3.1. Specifying Required Simulation Settings for Run Simulation (Batch Mode) 1.9.3.2. Optional Simulation Settings for Run Simulation (Batch Mode) 1.9.3.3. Launching Simulation with the Run Simulation Feature 1.9.3.4. Running RTL Simulation using Run Simulation 1.9.3.5. Output Directories and Files for Run Simulation
1.10. Using Precompiled Simulation Libraries x
1.10.1. Enabling Precompiled Simulation Libraries 1.10.2. Implementing Precompiled Simulation Libraries
2. Siemens EDA QuestaSim* Simulator Support x
2.1. Quick Start Example (QuestaSim* with Verilog) 2.2. QuestaSim* Simulator Guidelines 2.3. Using the Qrun Flow 2.4. QuestaSim* Simulation Setup Script Example 2.5. Sourcing QuestaSim* Simulator Setup Scripts 2.6. Unsupported Features 2.7. Siemens EDA QuestaSim* Simulator Support Revision History
2.2. QuestaSim* Simulator Guidelines x
2.2.1. Passing Parameter Information from Verilog HDL to VHDL 2.2.2. Viewing Simulation Messages 2.2.3. Generating Signal Activity Data for Power Analysis 2.2.4. Viewing Simulation Waveforms
2.3. Using the Qrun Flow x
2.3.1. Specifying Simulation File Generation Settings 2.3.2. Generating the Simulation Model and Setup Scripts 2.3.3. Generating the Testbench System 2.3.4. Generating Example Design Simulation Files 2.3.5. Recommendations for Using Qrun
3. Synopsys VCS* Support x
3.1. Quick Start Example (VCS with Verilog) 3.2. VCS Guidelines 3.3. VCS Simulation Setup Script Example 3.4. Sourcing Synopsys VCS* (3-Step) Simulator Setup Scripts 3.5. Sourcing Synopsys VCS* (2-Step) Simulator Setup Scripts 3.6. Synopsys VCS* and VCS MX Support Revision History
4. Aldec Active-HDL and Riviera-PRO Support x
4.1. Quick Start Example (Active-HDL VHDL) 4.2. Aldec Active-HDL and Riviera-PRO Guidelines 4.3. Using Simulation Setup Scripts 4.4. Sourcing Aldec ActiveHDL* or Riviera Pro* Simulator Setup Scripts 4.5. Aldec Active-HDL* and Riviera-PRO * Support Revision History
5. Cadence Xcelium* Parallel Simulator Support x
5.1. Using the Command-Line Interface 5.2. Generating Simulator Setup Script Templates 5.3. Sourcing Cadence Xcelium* Simulator Setup Scripts 5.4. Cadence Xcelium* Parallel Simulator Support Revision History
Answers to Top FAQs
1. FPGA Simulation Basics
2. Siemens EDA QuestaSim* Simulator Support
3. Synopsys VCS* Support
4. Aldec Active-HDL and Riviera-PRO Support
5. Cadence Xcelium* Parallel Simulator Support
6. Quartus® Prime Pro Edition User Guide Third-party Simulation Archive
A. Quartus® Prime Pro Edition User Guides

1.9.1.2. Simulation Flow Settings (EDA Tool Settings Page)

The simulation flow settings allow you to specify additional options for the automated simulation flow. Click Assignments > Settings > EDA Tool Settings > Simulation > Simulation Flow Settings to specify any of the following additional options.
Table 10.  Simulation Flow Settings (EDA Tool Settings Page) Settings Dialog Box
Name Setting Description
Clean previous simulation directory if exists

Off

On (Default)

 Allows you to clean (On) or retain (Off) the simulation directory created by the previous simulation run.
Command-line/batch mode

Off (Default)

On

Allows you to launch a third-party EDA tool in command-line mode (On) rather than opening the GUI (Off).
Compile options for VHDL IP RTL string Allows you to specify additional custom compilation options for one or more simulators to be applied on the IP VHDL RTL. For example:

questa=my_questa_options

vcs=my_vcs_options

activehdl=my_activehdl_options

xcelium=my_xcelium_options

rivierapro=my_activehdl_options
Compile options for VHDL Non-IP/User RTL string Allows you to specify additional custom compilation options for one or more simulators to be applied on the Non-IP VHDL RTL.
Compile options for Verilog IP RTL string Allows you to specify additional custom compilation options for one or more simulators to be applied on the IP Verilog RTL.
Compile options for Verilog Non-IP/User RTL string Allows you to specify additional custom compilation options for one or more simulators to be applied on the Non-IP Verilog RTL.
Compile options for both Verilog and VHDL IP RTL string Allows you to specify additional custom compilation options for one or more simulators to be applied on the IP Verilog and VHDL RTL.
Compile options for both Verilog and VHDL Non-IP/User RTL string Allows you to specify additional custom compilation options for one or more simulators to be applied on the non-IP Verilog and VHDL RTL.
Elaboration options string Allows you to specify additional custom simulation elaboration options for one or more simulators.
Simulation options string Allows you to specify additional custom simulation options for one or more simulators.
Simulation scripts generation only

Off (Default)

On

Allows you to generate only the command scripts for the third-party EDA tool without launching the simulator itself.

Select Off to launch the simulator using the Run Simulation feature.
Use relative paths for simulation Scripts

Off (Default)

On

If turned on, the simulation script specifies the location of your RTL files with relative paths, which allows designers to share projects between machines.

The relative path is subject to satisfying the following conditions:
  • The simulation output directory is inside the project directory. If output directory is outside, the relative path settings are not considered.
  • If an RTL file is placed outside the project directory, the simulation script does not use a relative path for that file.

An example of the behavior when this switch is turned on is as follows:

If your design includes a Verilog file called seq_det.v that is located in the same directory of your project, and your simulation script is located three levels deep from the directory of the project, your simulation script will have a line specifying a relative location for the file that includes a substring similar to the following string:

{../../../seq_det.v}
User precompiled simulation library mapping file (cds.lib) path for Xcelium

Off (default)

On

 Specifies the path to the cds.lib precompiled simulation mapping file for Xcelium.
User precompiled simulation library mapping file (library.cfg) path for Riviera-PRO

Off (default)

On

 Specifies the path to the library.cfg precompiled simulation mapping file for Riviera PRO.
User precompiled simulation library mapping file (modelsim.ini) path for QuestaSim

Off (default)

On

 Specifies the path to the modelsim.ini precompiled simulation mapping file for QuestaSim.
User precompiled simulation library mapping file (synopsys_sim.setup) path for VCS

Off (default)

On

 Specifies the path to the synopsys_sim.setup precompiled simulation mapping file for VCS.
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