Error Message Register Unloader Intel FPGA IP Core User Guide

Download PDF
ID 683866
Date 5/23/2018
Public
Document Table of Contents
Document Table of Contents x
1. Error Message Register Unloader Intel® FPGA IP Core User Guide
1. Error Message Register Unloader Intel® FPGA IP Core User Guide x
1.1. Features 1.2. IP Core Device Support 1.3. Resource Utilization and Performance 1.4. Functional Description 1.5. Parameter Settings 1.6. Installing and Licensing Intel® FPGA IP Cores 1.7. Customizing and Generating IP Cores 1.8. Document Revision History for Error Message Register Unloader Intel® FPGA IP IP Core User Guide
1.4. Functional Description x
1.4.1. Error Message Register 1.4.2. Signals 1.4.3. Timing
1.4.3. Timing x
1.4.3.1. IP Timing Behavior ( Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices) 1.4.3.2. All Other Device Timing
1.7. Customizing and Generating IP Cores x
1.7.1. IP Catalog and Parameter Editor 1.7.2. The Parameter Editor 1.7.3. Specifying IP Core Parameters and Options 1.7.4. Specifying IP Core Parameters and Options (Legacy Parameter Editors)
1.7.3. Specifying IP Core Parameters and Options x
1.7.3.1. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition)
1.7.4. Specifying IP Core Parameters and Options (Legacy Parameter Editors) x
1.7.4.1. IP Core Generation Output ( Intel® Quartus® Prime Standard Edition)
1. Error Message Register Unloader Intel® FPGA IP Core User Guide

1.4. Functional Description

Supported Intel® FPGA devices have an error message register that indicates the occurrence of a CRC error in the configuration RAM (CRAM). CRAM errors can occur because of a single event upset (SEU).

You can use the Error Message Register Unloader IP core's Avalon-ST logic interface to access the FPGA device EMR. For example, you can use the Error Message Register Unloader IP core with the Intel® FPGA Fault Injection and Intel® FPGA Advanced SEU Detection IP cores to access device EMR information.

The Error Message Register Unloader IP core monitors the device EMR. When hardware updates the EMR content, the IP core reads (or unloads) and de-serializes the EMR content. The IP core allows other logic (such as the Intel® FPGA Advanced SEU Detection IP core, Intel® FPGA Fault Injection IP core, or user logic) to access the EMR content simultaneously.

As shown in the esc1417477325834.html#esc1417477325834__image_fbb_3mm_gs, the Error Message Register Unloader IP core instantiates the CRC Error Verify IP core for some devices.

Note: For more information on SEU support for your FPGA device, refer to the device handbook’s SEU mitigation chapter.
Level Two Title