Error Message Register Unloader Intel FPGA IP Core User Guide

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ID 683866
Date 5/23/2018
Public

1. Error Message Register Unloader Intel® FPGA IP Core User Guide

Updated for:
Intel® Quartus® Prime Design Suite 18.0
The Error Message Register Unloader Intel® FPGA IP core (altera_emr_unloader) reads and stores data from the hardened error detection circuitry in supported Intel® FPGA devices. You can use the Error Message Register Unloader IP core's Avalon® Streaming ( Avalon® -ST) logic interface to read the device EMR.
Figure 1.  Error Message Register Unloader Block Diagram

When hardware updates the EMR content, the IP core reads (or unloads) and de-serializes the EMR content, and allows other logic (such as the Intel® FPGA Advanced SEU Detection IP core, Intel® FPGA Fault Injection IP core, or user logic) to access the EMR content simultaneously.

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