1. Error Message Register Unloader Intel® FPGA IP Core User Guide
|Intel® Quartus® Prime Design Suite 18.0|
When hardware updates the EMR content, the IP core reads (or unloads) and de-serializes the EMR content, and allows other logic (such as the Intel® FPGA Advanced SEU Detection IP core, Intel® FPGA Fault Injection IP core, or user logic) to access the EMR content simultaneously.
Did you find the information on this page useful?