Intel® FPGA SDK for OpenCL™ Pro Edition: Programming Guide

ID 683846
Date 10/04/2021

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5.2.8. Loop Speculation (speculated_iterations Pragma)

Use the speculated_iterations pragma to direct the Intel® FPGA SDK for OpenCL™ Offline Compiler to improve the performance of pipelined loops.

The speculated_iterations pragma is applied to loops and hence, it must appear directly before the loop (the same place as other loop pragmas) as shown in the following:

#pragma speculated_iterations k // where k >= 0

The Intel® FPGA SDK for OpenCL™ Offline Compiler generates hardware to run k extra iterations of the loop while ensuring that the extra iterations do not affect anything. This allows either reducing the II of the loop or increasing the fmax. The deciding factor is how quickly the exit condition of the loop is calculated. If the calculation takes many cycles, it is better to have speculated_iterations larger.

Remember: Extra iterations increase the time before the next invocation of the loop can begin. This may be a factor if the actual number of iterations of the loop is very small (less than 5 to 10 or similar). In this case, specify the #pragma speculated_iterations value as 0 to allow subsequent loop iterations to start immediately but at the cost of a larger II to allow more time to evaluate the exit condition. Refer to the Loop Analysis report in the HLD report to identify whether the exit condition is a bottleneck for II.