Quartus® Prime Pro Edition User Guide: Partial Reconfiguration

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ID 683834
Date 5/16/2025
Public
Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. Creating a Partial Reconfiguration Design 2. Partial Reconfiguration Solutions IP User Guide A. Quartus® Prime Pro Edition User Guides
1. Creating a Partial Reconfiguration Design x
1.1. What's New In This Version 1.2. Partial Reconfiguration Terminology 1.3. Partial Reconfiguration Process Sequence 1.4. Internal Host Partial Reconfiguration 1.5. External Host Partial Reconfiguration 1.6. Partial Reconfiguration Design Flow 1.7. Partial Reconfiguration Design Considerations 1.8. Hierarchical Partial Reconfiguration 1.9. Partial Reconfiguration Design Timing Analysis 1.10. Partial Reconfiguration Design Simulation 1.11. Partial Reconfiguration Design Debugging 1.12. Partial Reconfiguration Security ( Stratix® 10 and Agilex™ 7 Designs) 1.13. PR Bitstream Compression and Encryption ( Arria® 10 and Cyclone® 10 GX Designs) 1.14. Avoiding PR Programming Errors 1.15. Exporting a Version-Compatible Compilation Database for PR Designs 1.16. Creating a Partial Reconfiguration Design Revision History
1.6. Partial Reconfiguration Design Flow x
1.6.1. Step 1: Identify Partial Reconfiguration Resources 1.6.2. Step 2: Create Design Partitions 1.6.3. Step 3: Floorplan the Design 1.6.4. Step 4: Add the Partial Reconfiguration Controller IP 1.6.5. Step 5: Define Personas 1.6.6. Step 6: Create Revisions for Personas 1.6.7. Step 7: Compile the Base Revision and Export the Static Region 1.6.8. Step 8: Setup PR Implementation Revisions 1.6.9. Step 9: Program the FPGA Device
1.6.3. Step 3: Floorplan the Design x
1.6.3.1. Applying Floorplan Constraints Incrementally
1.6.4. Step 4: Add the Partial Reconfiguration Controller IP x
1.6.4.1. Adding the Partial Reconfiguration Controller IP 1.6.4.2. Adding the Partial Reconfiguration Controller Arria® 10/Cyclone 10 IP
1.6.7. Step 7: Compile the Base Revision and Export the Static Region x
1.6.7.1. Understanding PR Logic Utilization Reports
1.6.9. Step 9: Program the FPGA Device x
1.6.9.1. Generating PR Bitstream Files 1.6.9.2. Generating PR Bitstream Files 1.6.9.3. Partial Reconfiguration Bitstream Compatibility Checking 1.6.9.4. Raw Binary Programming File Byte Sequence Transmission Examples 1.6.9.5. Generating a Merged .pmsf File from Multiple .pmsf Files ( Arria® 10 and Cyclone® 10 GX Designs)
1.7. Partial Reconfiguration Design Considerations x
1.7.1. Partial Reconfiguration Design Guidelines 1.7.2. PR Design Timing Closure Best Practices 1.7.3. PR File Management 1.7.4. Evaluating PR Region Initial Conditions 1.7.5. Creating Wrapper Logic for PR Regions 1.7.6. Creating Freeze Logic for PR Regions 1.7.7. Resetting the PR Region Registers 1.7.8. Promoting Global Signals in a PR Region 1.7.9. Planning Clocks and other Global Routing 1.7.10. Implementing Clock Enable for On-Chip Memories
1.7.3. PR File Management x
1.7.3.1. Method 1 (Preferred): Specify Unique Entity and File Names for Each Persona 1.7.3.2. Method 2: Set QSF Assignment for a Parameterized PR Persona
1.7.8. Promoting Global Signals in a PR Region x
1.7.8.1. Viewing Row Clock Region Boundaries
1.7.10. Implementing Clock Enable for On-Chip Memories x
1.7.10.1. Clock Gating
1.8. Hierarchical Partial Reconfiguration x
1.8.1. Using Parent QDB Files from Different Compiles
1.9. Partial Reconfiguration Design Timing Analysis x
1.9.1. Running Timing Analysis on Aggregate Revisions
1.10. Partial Reconfiguration Design Simulation x
1.10.1. Partial Reconfiguration Simulation Flow 1.10.2. Simulating PR Persona Replacement
1.10.2. Simulating PR Persona Replacement x
1.10.2.1. altera_pr_persona_if Module 1.10.2.2. altera_pr_wrapper_mux_out Module 1.10.2.3. altera_pr_wrapper_mux_in Module
1.11. Partial Reconfiguration Design Debugging x
1.11.1. Debugging PR Designs with the Signal Tap Logic Analyzer 1.11.2. Instantiating the Configuration Reset Release Endpoint to Debug Logic IP
1.12. Partial Reconfiguration Security ( Stratix® 10 and Agilex™ 7 Designs) x
1.12.1. PR Bitstream Security Validation ( Stratix® 10 and Agilex™ 7 Designs) 1.12.2. PR Bitstream Authentication ( Stratix® 10 and Agilex™ 7 Designs) 1.12.3. PR Bitstream Encryption ( Stratix® 10 and Agilex™ 7 Designs)
1.13. PR Bitstream Compression and Encryption ( Arria® 10 and Cyclone® 10 GX Designs) x
1.13.1. Generating an Encrypted PR Bitstream ( Arria® 10 or Cyclone® 10 GX Designs) 1.13.2. Clock-to-Data Ratio for Bitstream Encryption and Compression ( Arria® 10 or Cyclone® 10 GX Designs) 1.13.3. Data Compression Comparison
1.15. Exporting a Version-Compatible Compilation Database for PR Designs x
1.15.1. Version-Compatible Database Flow for PR Designs 1.15.2. Generating a Version-Compatible Compilation Database for PR Designs
2. Partial Reconfiguration Solutions IP User Guide x
2.1. Internal and External PR Host Configurations 2.2. Partial Reconfiguration Controller IP 2.3. Partial Reconfiguration Controller Arria® 10/Cyclone® 10 IP 2.4. Partial Reconfiguration External Configuration Controller IP 2.5. Partial Reconfiguration Region Controller IP 2.6. Avalon® -MM Partial Reconfiguration Freeze Bridge IP 2.7. Avalon® -ST Partial Reconfiguration Freeze Bridge IP 2.8. Generating and Simulating Altera* IP 2.9. Quartus® Prime Pro Edition User Guide: Partial Reconfiguration Archive 2.10. Partial Reconfiguration Solutions IP User Guide Revision History
2.2. Partial Reconfiguration Controller IP x
2.2.1. Memory Map 2.2.2. Parameters 2.2.3. Ports 2.2.4. Timing Specifications 2.2.5. PR Error Recovery 2.2.6. Secure Device Manager Firmware Error Reporting
2.2.5. PR Error Recovery x
2.2.5.1. PR Error Recovery Timing Specifications
2.2.6. Secure Device Manager Firmware Error Reporting x
2.2.6.1. SDM Firmware Error Reporting Timing Specification
2.3. Partial Reconfiguration Controller Arria® 10/Cyclone® 10 IP x
2.3.1. Agent Interface 2.3.2. Reconfiguration Sequence 2.3.3. Interrupt Interface 2.3.4. Parameters 2.3.5. Ports 2.3.6. Timing Specifications 2.3.7. PR Control Block and CRC Block Verilog HDL Manual Instantiation 2.3.8. PR Control Block and CRC Block VHDL Manual Instantiation 2.3.9. PR Control Block Signals 2.3.10. Configuring an External Host for Arria® 10 or Cyclone® 10 GX Designs
2.3.4. Parameters x
2.3.4.1. Error Detection CRC Requirements
2.3.8. PR Control Block and CRC Block VHDL Manual Instantiation x
2.3.8.1. PR Control Block and CRC Block VHDL Component Declaration
2.3.9. PR Control Block Signals x
2.3.9.1. PR Control Block Signal Timing Diagrams
2.4. Partial Reconfiguration External Configuration Controller IP x
2.4.1. Parameters 2.4.2. Ports 2.4.3. Partial Reconfiguration External Controller IP Timing Specifications 2.4.4. Configuring an External Host ( Stratix® 10 or Agilex™ FPGA Portfolio Devices)
2.5. Partial Reconfiguration Region Controller IP x
2.5.1. Registers 2.5.2. Parameters 2.5.3. Ports
2.6. Avalon® -MM Partial Reconfiguration Freeze Bridge IP x
2.6.1. Parameters 2.6.2. Interface Ports
2.7. Avalon® -ST Partial Reconfiguration Freeze Bridge IP x
2.7.1. Parameters 2.7.2. Ports
2.8. Generating and Simulating Altera* IP x
2.8.1. Specifying the IP Parameters and Options ( Quartus® Prime Pro Edition) 2.8.2. Running the Freeze Bridge Update script 2.8.3. IP Core Generation Output ( Quartus® Prime Pro Edition) 2.8.4. Arria® 10 and Cyclone® 10 GX PR Control Block Simulation Model 2.8.5. Generating the PR Persona Simulation Model 2.8.6. Secure Device Manager Partial Reconfiguration Simulation Model
2.8.6. Secure Device Manager Partial Reconfiguration Simulation Model x
2.8.6.1. Monitoring the SDM 2.8.6.2. Simulating Unknown Outputs and Persona Activation 2.8.6.3. Simulation RBF Required Word Sequence
Answers to Top FAQs
1. Creating a Partial Reconfiguration Design
2. Partial Reconfiguration Solutions IP User Guide
A. Quartus® Prime Pro Edition User Guides

2. Partial Reconfiguration Solutions IP User Guide

The Quartus® Prime Pro Edition software includes the following Altera* IP cores that simplify partial reconfiguration implementation.

Instantiate one or more of these IP cores to implement handshake and freeze logic for PR functionality in your design. Alternatively, create your own PR handshake and freeze logic that interfaces with the PR region.

Table 11.  Partial Reconfiguration IP Cores
Altera* IP Description Usage

Partial Reconfiguration Controller IP

Dedicated IP component that sends the partial reconfiguration bitstream for Stratix® 10 and Agilex™ FPGA Portfolio devices. The PR bitstream performs reconfiguration by adjusting CRAM bits in the FPGA.

One instance per Stratix® 10 or Agilex™ FPGA Portfolio device
Partial Reconfiguration External Configuration Controller IP IP component that supports Stratix® 10 and Agilex™ FPGA Portfolio device partial reconfiguration via an external source over dedicated PR pins. One instance per Stratix® 10 or Agilex™ FPGA Portfolio device for external configuration

Partial Reconfiguration Controller Arria® 10/Cyclone 10 IP

Dedicated IP component that sends the partial reconfiguration bitstream to the Arria® 10 or Cyclone® 10 GX device. The PR bitstream performs reconfiguration by adjusting CRAM bits in the FPGA.

One instance per Arria® 10 or Cyclone® 10 GX device for internal or external configuration.

Partial Reconfiguration Region Controller IP

Provides a standard Avalon® memory-mapped interface to the block that controls handshaking with the PR region. Ensures that PR region stops, resets, and restarts, according to the PR handshake.

One instance per PR region.

Avalon® -MM Partial Reconfiguration Freeze Bridge IP

Provides freeze capabilities to the PR region for Avalon® memory-mapped interfaces.

One instance for each interface in each PR region.

Avalon® -ST Partial Reconfiguration Freeze Bridge IP

Provides freeze capabilities to the PR region for Avalon® streaming interfaces.

One instance for each interface in each PR region.

Section Content
Internal and External PR Host Configurations
Partial Reconfiguration Controller IP
Partial Reconfiguration Controller Arria® 10/Cyclone® 10 IP
Partial Reconfiguration External Configuration Controller IP
Partial Reconfiguration Region Controller IP
Avalon -MM Partial Reconfiguration Freeze Bridge IP
Avalon -ST Partial Reconfiguration Freeze Bridge IP
Generating and Simulating Altera IP
Quartus Prime Pro Edition User Guide: Partial Reconfiguration Archive
Partial Reconfiguration Solutions IP User Guide Revision History

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