XAUI PHY Release Notes

ID 683816
Date 5/08/2017
Public

1.3. XAUI PHY IP Core v14.0 Arria 10 Revision History

Table 3.  v14.0 Arria 10 Edition August 2014
Description Impact
Added support for Arria 10 devices. To use the XAUI PHY IP core for Arria 10 devices, you must instantiate an external transmit PLL. You can only use the ATX PLL IP core with the XAUI PHY IP core for Arria 10 devices. -
Added Enable dynamic reconfiguration parameter. -
Removed the following parameters:
  • PLL type.
  • External PMA control and configuration.
-
Added new port to enable connectivity with an external transmit PLL and with the dynamic reconfiguration interface. Refer to the Arria 10 Transceiver PHY User Guide parameter and port descriptions. -
The XAUI PHY IP core does not support NCSIM simulator. You will see an error message during elaboration. -
The XAUI PHY IP core does not support VHDL. You will get a compilation error when you simulate the XAUI PHY IP core generated in VHDL. You must generate this IP core in Verilog. -

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