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1.5. Compiling and Testing the Design
- Ensure that the hardware design example generation is complete.
- Open quartus/sdi_ii_c10_demo.qpf.
- Click .
- Open the Clock Controller parameter editor, and set the clock frequency.
SDI II Design Examples Si570 (Y2) Tab Si5332 (U64) Tab HD/3G-SDI single rate and triple rate Parallel loopback without external VCXO designs Set Target Frequency to 148.5 MHz. Set OUT1 frequency to 100 MHz. Serial loopback designs Set Target Frequency to 148.3516 MHz if Dynamic Tx clock switching is enabled. Set OUT1 frequency to 148.5 MHz Multi rate Parallel loopback with external VCXO designs Set Target Frequency to 297 MHz. Set OUT1 frequency to 148.5 MHz; if you set the Rx core clock (rx_coreclk) frequency parameter in the IP tab to 148.5/148.35 MHz. Serial loopback designs Set Target Frequency to 296.7033 MHz if Dynamic Tx clock switching is enabled. Set OUT1 frequency to 148.5 MHz; if you set the Rx core clock (rx_coreclk) frequency parameter in the IP tab to 148.5/148.35 MHz.Figure 5. Si570 (Y2) Tab in the Clock Controller GUIFigure 6. Si5332 (U64) Tab in the Clock Controller GUI
- After successful compilation, the Intel® Quartus® Prime Pro Edition software generates a .sof file in your specified directory.
- Configure the selected Intel® Cyclone® 10 GX device on the development board using the generated .sof file ( ).
- For serial loopback designs, open the System Console to control the internal video pattern generator. Click
.Note: Close the Clock Controller GUI and the Programmer window before you open the System Console.
- After the initialization, type source ../hwtest/tpg_ctrl.tcl in the System Console to open the pattern generator control user interface. Select your desired video format.
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