CORDIC Intel® FPGA IP User Guide

ID 683808
Date 1/16/2024

1.6. Document Revision History for the CORDIC Intel FPGA IP User Guide

Document Version Intel® Quartus® Prime Version Changes
2024.01.16 23.2 Corrected Atan2 Function Signals output a width to w OUT= F OUT+3.
2023.07.07 23.2
  • Removed unsigned option in Vector Rotate Parameters
  • In Vector Rotate Signals table:
    • Removed the unsigned input [0,1] from x,y.

      Removed the unsigned input row for x0, y0.

      Changed signed input for x0, y0 to signed output.

2023.05.08 17.0 Initial release.