HDMI Intel® FPGA IP User Guide

ID 683798
Date 10/02/2023

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5.9. Variable Refresh Rate (VRR) and Auto Low Latency Mode (ALLM)

HDMI TX core can support Variable Refresh Rate (VRR) transport as described in HDMI 2.1 specification. Section 7.6. VRR involves modification of the video vertical blanking timing, which is external to the HDMI TX core. After user generates the video with VRR transport, HDMI TX core is able to transmit this video through the FRL packets.

User can enable the Auto Low Latency Mode through the ALLM_Mode field (HF-VSI packet bye 5, bit 1). For the HDMI Forum-VSI InfoFrame (HF-VSIF) transmission, use external VSI by asserting control bit (info_vsi[61]) to 1 and send the data through the Auxiliary Data Port instead of info_vsi sidebands. Refer to HDMI 2.1 specification Section 10.2 HDMI Forum Vendor Specific InfoFrame for more information.