1. Stratix® 10 High-Speed LVDS I/O Overview
2. Stratix® 10 High-Speed LVDS I/O Architecture and Features
3. Stratix 10 High-Speed LVDS I/O Design Considerations
4. Stratix® 10 High-Speed LVDS I/O Implementation Guides
5. LVDS SERDES Intel® FPGA IP References
6. Stratix® 10 High-Speed LVDS I/O User Guide Archives
7. Document Revision History for the Stratix® 10 High-Speed LVDS I/O User Guide
3.1. PLLs and Clocking for Stratix® 10 Devices
3.2. Source-Synchronous Timing Budget
3.3. Guideline: LVDS SERDES IP Core Instantiation
3.4. Guideline: LVDS SERDES Pin Pairs for Soft-CDR Mode
3.5. Guideline: LVDS Transmitters and Receivers in the Same I/O Bank
3.6. Guideline: LVDS SERDES Limitation for Stratix® 10 GX 400, SX 400, and TX 400
3.1.1. Clocking Differential Transmitters
3.1.2. Clocking Differential Receivers
3.1.3. Guideline: LVDS Reference Clock Source
3.1.4. Guideline: Use PLLs in Integer PLL Mode for LVDS
3.1.5. Guideline: Use High-Speed Clock from PLL to Clock LVDS SERDES Only
3.1.6. Guideline: Pin Placement for Differential Channels
3.1.7. LVDS Interface with External PLL Mode
4.3.2. FPGA Timing Analysis
When you generate the LVDS SERDES IP, the IP generates the SERDES hardware clock settings and the core clock for IP timing analysis.
Clock | Clock Name |
---|---|
Core clock | <pll_instance_name>_*_outclk[*] |
LVDS SERDES fast clock | <pll_instance_name>_*_lvds_clk[*] |
Clock | Clock Name |
---|---|
Core clock | <lvds_instance_name>_core_ck_name_<channel_num> |
DPA fast clock | <lvds_instance_name>_dpa_ck_name_<channel_num> |
To ensure proper timing analysis, instead of multicycle constraints, the IP creates clock settings at rx_out in the following format:
- For rising edge data— <lvds_instance_name>_core_data_out_<channel_num>_<bit>
- For falling edge data— <lvds_instance_name>_core_data_out_<channel_num>_<bit>_neg
With these proper clock settings, the Timing Analyzer can correctly analyze the timing of the LVDS SERDES–core interface transfer and within the core transfer.