6.2.6. OCT Intel® FPGA IP Architecture
OCT Intel FPGA IP Power-Up Mode Interfaces
- One input interface connecting the FPGA RZQ pad to the OCT block
- One output interface that connects to the I/O buffers.
OCT Intel FPGA IP User Mode OCT
The FPGA core initiates a calibration request to the OCT IP by asserting the calibration_request signal to high for at least 2 µs. The OCT IP asserts the ack_recal signal to the core to indicate that the IP has received the request.
You can only use the OCT IP in user mode with the GPIO IP. Connect the terminationcontrol signal from the GPIO IP to the ser_data signal in the OCT IP using RTL connections or TERMINATION_CONTROL_BLOCK .qsf assignment.