5G Polar Intel® FPGA IP User Guide

ID 683766
Date 9/30/2020
Public

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1.1. 5G Polar Intel® FPGA IP Features

  • Complies with the 3GPP 5G Polar specification
  • Run-time configurable code block length, code rate, frozen bit, and parity check bit locations with optional reconfiguration for each code block
  • Code block length from 32, 64, 128, 256, 512 and 1024
  • Optional CRC, including CRC6, 11, 16, 24a, 24b and 24c
  • Optional DCI format with RNTI scrambling for CRC24c
  • Optional interleaving and deinterleaving
  • Successive cancellation list decoding scheme, compile-time configurable list size, from L=4 or L=8
  • Decoder output buffering allows the downstream to receive result while the decoder processes the next data block
  • C and MATLAB bit-accurate models for performance simulation and RTL test vector generation
  • System Verilog HDL testbench
  • Avalon® streaming input and output interfaces

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