Intel Agilex® 7 Clocking and PLL User Guide: F-Series and I-Series

ID 683761
Date 7/13/2023

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Document Table of Contents

2.1.1. Clock Network Architecture

Each F-Series and I-Series device is divided into a number of evenly sized clock sectors.

Figure 1. Clock Sector Floorplan for F-Series and I-Series DevicesThis figure shows an example of the clock sectors in an F-Series and I-Series device, which is implemented as an array of sectors—5 rows and 6 columns in this example. I/O banks are at the top and bottom of the F-Series and I-Series device.