Low Latency 100G Ethernet Intel® Stratix® 10 FPGA IP Core Release Notes

ID 683755
Date 9/24/2018

1.2. Low Latency 100G Ethernet Intel® Stratix® 10 FPGA IP Core v18.0

Table 2.  Version 18.0
Description Impact Notes

Added support for local fault and remote fault monitoring and statistics.

Added support for optional IEEE 802.3 Clause 31 Ethernet flow control and priority-based flow control.

Added support for 322.265625 MHz PHY reference frequency.

Transceiver reconfiguration clock and control and status interface clock changed from 100 - 125 MHz to 100 - 162 MHz.

Added parameters for Low Latency 100G Ethernet Intel FPGA IP core:
  • Enable MAC Flow Control - Turning on this parameter enables the flow control mechanism.
  • Number of queues in priority flow control - Number of distinct priority queues for priority-based flow control.
  • Enable link fault generation - Turning on this parameter includes link fault signaling modules and relevant signals.

Added support for hardware design example generation using Stratix 10 GX Transceiver Signal Integrity Development Kit.

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