Turbo Intel® FPGA IP User Guide

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ID 683734
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the Turbo Intel® FPGA IP 2. Getting Started with the Turbo Intel® FPGA IP 3. Parameter Settings 4. Turbo Intel® FPGA IP Functional Description A. Turbo IP User Guide Document Archives 5. Document Revision History for Turbo Intel® FPGA IP User Guide
1. About the Turbo Intel® FPGA IP x
1.1. Turbo Intel® FPGA IP Features 1.2. Turbo Intel® FPGA IP Device Family Support 1.3. Turbo IP Performance and Resource Utilization 1.4. Turbo Code Licensing Disclaimer 1.5. Release Information
2. Getting Started with the Turbo Intel® FPGA IP x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. IP Catalog and Parameter Editor 2.3. Specifying the IP Core Parameters and Options 2.4. Simulating Intel® FPGA IP Cores 2.5. Simulating the IP with the RTL Simulator 2.6. Simulating the Turbo IP with the C-Model 2.7. Simulating the Turbo IP with MATLAB
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. Turbo IP Timeout Behavior
2.3. Specifying the IP Core Parameters and Options x
2.3.1. IP Core Generation Output ( Quartus® Prime Pro Edition)
4. Turbo Intel® FPGA IP Functional Description x
4.1. Turbo Encoder 4.2. Turbo Decoder 4.3. 4.4. Turbo Throughput
4.1. Turbo Encoder x
4.1.1. Turbo Encoder Data Format 4.1.2. Turbo Encoder Latency Calculation
4.2. Turbo Decoder x
4.2.1. Turbo Decoder Data Format 4.2.2. CRC24A or CRC24B Early Termination 4.2.3. Decoder Latency Calculation 4.2.4. Error Correction Performance for the Turbo Decoder
1. About the Turbo Intel® FPGA IP
2. Getting Started with the Turbo Intel® FPGA IP
3. Parameter Settings
4. Turbo Intel® FPGA IP Functional Description
A. Turbo IP User Guide Document Archives
5. Document Revision History for Turbo Intel® FPGA IP User Guide

4.2.4. Error Correction Performance for the Turbo Decoder

Figure 9. BER (bit error rate) Curve of LTE turbo decoder over AWGN channels, where N dec= 8, W LLR= 6, and I= 8Block sizes (K) are 6144, 4096, 2048, 1024, 512, 256, 128, 64 respectively (from left to right).
Figure 10. BLER (block error rate) Curve of LTE turbo decoder over AWGN channels, where N dec= 8, W LLR= 6, and I= 8Block sizes (K) are 6144, 4096, 2048, 1024, 512, 256, 128, 64 respectively (from left to right).
Figure 11. BER Curve of UMTS turbo decoder over AWGN channels, where N dec= 4, W LLR= 6, and I= 8Block sizes (K) are 5144, 2048, 1024, 512, 256, 128, 64 respectively (from left to right).
Figure 12. BLER Curve of UMTS turbo decoder over AWGN channels, where N dec= 4, W LLR= 6, and I= 8Block sizes (K) are 5144, 2048, 1024, 512, 256, 128, 64 respectively (from left to right).
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