Intel® Stratix® 10 E-Tile Transceiver Native PHY IP Release Notes

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ID 683728
Date 7/10/2020
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1. Intel® Stratix® 10 E-Tile Transceiver Native PHY IP Release Notes
1. Intel® Stratix® 10 E-Tile Transceiver Native PHY IP Release Notes x
1.1. Intel® Stratix® 10 E-Tile Transceiver Native PHY IP Release Notes v20.2.0 1.2. Intel® Stratix® 10 E-Tile Transceiver Native PHY IP Release Notes v20.1.0 1.3. Intel® Stratix® 10 E-Tile Transceiver Native PHY IP Release Notes v19.4.0 1.4. Intel® Stratix® 10 E-Tile Transceiver Native PHY IP Release Notes v19.3.0
1. Intel® Stratix® 10 E-Tile Transceiver Native PHY IP Release Notes

1.1. Intel® Stratix® 10 E-Tile Transceiver Native PHY IP Release Notes v20.2.0

Table 1.  v20.1.0 2020.07.10
Intel® Quartus® Prime Version Description Impact
20.2

Updated the functionality for unused transceiver channels—the Native PHY IP allows you to specify the reference clock pin assignment and reference clock frequency explicitly for each bank with unused channels to be protected in the design.

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