1.12. Latest Known Intel® Quartus® Prime Software Issues
|For some early-specification Intel® Agilex™ devices, the JTAG disable security fuse is not supported by the device but the Intel® Quartus® Prime Programmer Version 21.4 allows you to program the fuse on these devices.||For a list of affected devices, refer to Intel® Agilex™ Known Issue List .
If your device is affected, do not use the Intel® Quartus® Prime Programmer Version 21.4 to program the JTAG disable security fuse on your device.
|For the PHY Lite for Parallel Interfaces Intel Agilex FPGA IP, timing analysis results for periphery to core (P2C) transfer might not be reliable. As a result, you might have be functional-failures, bit-errors, or both on P2C paths.||
This issue only affects P2C transfers within PHY Lite for Parallel Interfaces Intel Agilex FPGA IP.
For details and the availability of a fix, refer to " Why am I seeing intermittent bit-errors on the PHY Lite for Parallel Interfaces Intel® Agilex™ FPGA IP input path designs? " in the Intel FPGA Knowledge Base.
|Some Intel® Stratix® 10 devices are incorrectly blocked from using simple quad-port memory mode.||For details and the availability of a fix, refer to " Why are there functional errors in my simple quad port mode M20K RAM? " in the Intel FPGA Knowledge Base.|
You can find known issue information for previous versions of the Quartus® Prime software on the Intel FPGA Knowledge Base web page.
Information about known software issues that affect previous versions of the Quartus® II software is available on the Intel® Quartus® Prime and Quartus II Software Support web page.
Information about issues affecting the Intel® FPGA IP Library is available in the release notes for each IP. You can find the IP release notes on the Intel® FPGAs and Programmable Devices Release Notes web page.