Why are there intermittent bit errors on the PHY Lite for Parallel Interfaces IP for Agilex™ 7 FPGA and Agilex™ 9 FPGA input path designs?

Due to a problem in the Quartus® Prime Pro Edition Software version 21.4, you might find functional failures or bit errors on Periphery-to-Core- Core (P2C) paths when using the PHY Lite for Parallel Interfaces IP for Agilex™ 7 and Agilex™ 9 FPGA. This is because the timing of the P2C transfer paths is not analyzed.

This problem only affects P2C transfers within PHY Lite for Parallel Interfaces IP for Agilex™ 7 FPGA and Agilex™ 9 FPGA.

A patch is available to fix this problem for the Quartus® Prime Pro Edition software version 21.4.
Download and install patch 0.02 from the link below.

For Quartus® Prime Pro Edition software version 21.4

• Download patch 0.02 for Windows (quartus-21.4-0.02-windows.exe)
• Download patch 0.02 for Linux (quartus-21.4-0.02-linux.run)
• Download the Readme for patch 0.02 (quartus-21.4-0.02-readme.txt)

This problem is fixed beginning with the Quartus® Prime Pro Edition Software version 22.1.