Why are there intermittent bit-errors on the PHY Lite for Parallel Interfaces Intel® Agilex™ FPGA IP input path designs?

Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 21.4, you may find functional failures or bit-errors on Periphery-to- Core (P2C) paths when using the PHY Lite for Parallel Interfaces Intel® Agilex™ FPGA IP. This is because the timing of the P2C transfers paths is not analyzed.

This problem only affects P2C transfers within PHY Lite for Parallel Interfaces Intel® Agilex™ FPGA IP.

There is no workaround to this problem but a patch is scheduled to be released.

This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.