Article ID: 000088809 Content Type: Troubleshooting Last Reviewed: 01/07/2022

Why are there intermittent bit-errors on the PHY Lite for Parallel Interfaces Intel® Agilex™ FPGA IP input path designs?

Environment

  • Intel® Quartus® Prime Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 21.4, you may find functional failures or bit-errors on Periphery-to- Core (P2C) paths when using the PHY Lite for Parallel Interfaces Intel® Agilex™ FPGA IP. This is because the timing of the P2C transfers paths is not analyzed.

    This problem only affects P2C transfers within PHY Lite for Parallel Interfaces Intel® Agilex™ FPGA IP.

    Resolution

    There is no workaround to this problem but a patch is scheduled to be released.

    This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.

    Related Products

    This article applies to 1 products

    Intel® Agilex™ FPGAs and SoC FPGAs

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