1.1. New Features and Enhancements
Intel® Quartus® Prime Pro Edition Software Version 21.3 includes functional and security updates. Keep your software up-to-date and follow the technical recommendations that help improve the security of your Intel® Quartus® Prime installation.
- Added support for the following simulation software:
- Questa*-Intel® FPGA Edition
This software replaces ModelSim*-Intel® FPGA Edition.
- Questa*-Intel® FPGA Starter Edition
This software replaces ModelSim*-Intel® FPGA Starter Edition.
- Questa*-Intel® FPGA Edition
- Introduced the Nios® V/m soft processor that is based on the open-source RISC-V architecture
New Platform Designer Features and Enhancements
- Added ability to preserve signals during compilation. Preserved signals remain available for debugging in Signal Tap Logic Analyzer and are not optimized away.
- Added the System Diff Tool that highlights the differences between two Platform Designer systems or IP components (.qsys or .ip files).
- Added the ability to launch the BSP Editor from Platform Designer in integrated mode for the Nios® V soft processor. In integrated mode, BSP Editor automatically updates for any changes that you make to your system in Platform Designer.
- Added the ability to change Platform Designer GUI font sizes.
New Synthesis Features and Enhancements
- Added support for the following VHDL-2019 features:
- Conditional analysis tool directives (IEEE Std 1076-2019 Section 24.2)
- Interface declarations (IEEE Std 1076-2019 Section 6.5)
- Enhanced synthesis reports as follows:
- Added Hierarchies Optimized Away During Sweep report to provide information about entities that were optimized away during synthesis.
- Added Warning Messages summary reports to see the types of warning messages generated for each source file.
- Added Preserve for Debug Assignments report to provide information about RTL nodes that were explicitly marked to preserve the signals through compilation.
New Compiler Features and Enhancements
- Added the Fast Functional Test compilation mode.
This compilation mode can help you save time early in your design cycle when you are testing algorithmic logic or other logic that is not critical to the fMAX of your design.
- Added ability to preserve signals during compilation. Preserved signals remain available for debugging and are not optimized away.
- Reduced the memory requirements for processing Intel® Agilex™ designs:
- Memory requirements for processing designs that target AGFA012, AGFA014, AGFB012, and AGFB014 devices are now 32 GB, reduced from 64 GB.
- Memory requirements for processing designs that target AGFA022, AGFB022, AGFA027, and AGFB027devices are now 64 GB, reduced from 72 GB.
- Enhanced the security of Intel® Agilex™ devices with Attestation via JTAG command and FPGA mailbox.
New Timing Analyzer Features and Enhancements
- Enhanced Timing Analyzer reports as follows:
- Added Report Clock Network report to identify and evaluate advanced clock structures, such as clock muxes, clock gates, and clock dividers.
- Added Report Exceptions Reachability report to show the scope of exception constraints in your project.
- Added Report Data Delay report that shows the worst-case slack for the datapath delay exception for a given path.
New Design Assistant Features and Enhancements
- Enhanced Design Assistant with new rule checks and improved run time for some existing checks.
New Signal Tap Logic Analyzer Features and Enhancements
- (Beta) Added the ability to use RTL simulation tools using data captured by Signal Tap Logic Analyzer:
- Added support for using Signal Tap signal and acquisition data directly in your simulation software for enhanced visibility into the internal signal in a design hierarchy.
- Added support for transforming Signal Tap data into an RTL simulation testbench. This support helps expand the signal states in the simulation tool beyond the data that Signal Tap captures.
- Added the ability to make iterative changes to the post-fit Signal Tap nodes that you want to target, without rerunning full compilation to implement the changes.
New Advanced Link Analyzer Features and Enhancements
- Updated support for Agilex F-tile and R-tile
- Added beta-level support for forward clocking IBIS-AMI simulation support
- Added low latency FEC support
- Updated PAM4 jitter analysis capabilities
- Updated channel analysis and compliance test for 106G Ethernet and 112G OIF-CEI standards
- Extended device ERL compliance test support
New Power and Thermal Calculator Features and Enhancements
- For Intel® Agilex™ devices, added Typical to the Power characteristics field to enable power characterization for typical operation of your design in addition to the power characterization of maximum operation of your design.
- For Intel® Stratix® 10 devices with high-bandwidth memory (HBM), updated power models to reflect more realistic use cases, rather than worst-case power consumption.