Configuring Altera FPGAs

ID 683692
Date 12/15/2014

1.1. Device Configuration Overview for Passive Schemes

During device operation, Altera FPGAs store configuration data in SRAM cells. Because SRAM memory is volatile, the SRAM cells must be loaded with configuration data each time the device powers up. After the device is configured, its registers and I/O pins must be initialized. After initialization, the device enters user mode for in-system operation.
Figure 1. Configuration Cycle Waveform

The low-to-high transition of nCONFIG on the FPGA begins the configuration cycle. The configuration cycle consists of 3 stages—reset, configuration, and initialization. While nCONFIG is low, the device is in reset. When the device comes out of reset, nCONFIG must be at a logic high level in order for the device to release the open-drain nSTATUS pin. After nSTATUS is released, it is pulled high by a pull-up resistor and the FPGA is ready to receive configuration data. Before and during configuration, all user I/O pins are tri-stated. Stratix® series, Arria® series, and Cyclone® series have weak pull-up resistors on the I/O pins which are on, before and during configuration.

To begin configuration, nCONFIG and nSTATUS must be at a logic high level. You can delay configuration by holding the nCONFIG low. The device receives configuration data on its DATA0 pins. Configuration data is latched into the FPGA on the rising edge of DCLK. After the FPGA has received all configuration data successfully, it releases the CONF_DONE pin, which is pulled high by a pull-up resistor. A low to high transition on CONF_DONE indicates configuration is complete and initialization of the device can begin.

An optional INIT_DONE pin is available, which signals the end of initialization and the start of user mode. During initialization, internal logic and I/O registers are initialized and I/O buffers are enabled. When initialization is finished, the INIT_DONE pin is released and pulled high by an external pull-up resistor. After entering user mode, the user I/O pins will no longer have a weak pull up and will function as assigned in your design. After configuration, you must not leave the DATA0 pins floating. Drive the pin high or low, whichever is convenient, on your board.

You can initiate a reconfiguration by toggling the nCONFIG pin from high to low and then back to high. When nCONFIG is pulled low, nSTATUS and CONF_DONE are also pulled low and all I/O pins are tri-stated. After nCONFIG and nSTATUS return to a logic high level, configuration begins.

Figure 2. Configuration Cycle State Machine

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