Arria 10 Transceiver CMU PLL IP Core Release Notes

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ID 683690
Date 10/31/2016
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1. Arria 10 Transceiver CMU PLL IP Core Release Notes
1. Arria 10 Transceiver CMU PLL IP Core Release Notes x
1.1. Arria 10 Transceiver CMU PLL IP Core v15.1 Revision History 1.2. Arria 10 Transceiver CMU PLL IP Core v15.0 Revision History 1.3. Arria 10 Transceiver CMU PLL IP Core v14.1 Revision History 1.4. Arria 10 Transceiver CMU PLL IP Core v14.0 Revision History 1.5. Arria 10 Transceiver CMU PLL IP Core v13.1 Revision History
1. Arria 10 Transceiver CMU PLL IP Core Release Notes

1.4. Arria 10 Transceiver CMU PLL IP Core v14.0 Revision History

Table 4.  v14.0 Arria 10 Edition August 2014
Description Impact
Upgraded to support the new IP Catalog. For more information about the IP Catalog, refer to IP Catalog and Parameter Editor in Introduction to Altera IP Cores. -
Added support for Embedded debug feature. This feature enables you to write to the PLL control registers and read from status registers for the PLL instances in the design. This feature is available under the Dynamic Reconfiguration tab. -
Added preset GX 2500 Mbps Single Channel for GX mode. -
Changed the IP core to expose the pll_cal_busy port to the top level. -
Changed the documentation link in IP Parameter Editor to refer to the Arria 10 Transceiver PHY User Guide. -
Enhanced user warnings and information messages. -
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