AN 954: Hierarchical Partial Reconfiguration Tutorial: for the Intel Agilex® 7 FPGA Development Board

ID 683687
Date 1/16/2024
Public

Step 5: Defining Personas

This reference design defines five separate personas for the parent and child PR partitions. To define and include the personas in your project:

  1. Create four SystemVerilog files, blinking_led_child.sv, blinking_led_child_slow.sv, blinking_led_child_empty.sv, and blinking_led_slow.sv in your working directory for the five personas.
    Note: If you create the SystemVerilog files from the Intel® Quartus® Prime Text Editor, disable the Add file to current project option when saving the files.
    Table 2.  Reference Design Personas
    File Name Description Code
    blinking_led_child.sv Default persona for the child-level design
    `timescale 1 ps / 1 ps
    `default_nettype none
    
    module blinking_led_child (
    
       // clock
       input wire clock,
       input wire [31:0] counter,
    
       // Control signals for the LEDs
       output wire led_three_on
    
    );
       localparam COUNTER_TAP = 23;
       reg led_three_on_r;
    
       assign led_three_on   = led_three_on_r;
       
       always_ff @(posedge clock) begin
          led_three_on_r   <= counter[COUNTER_TAP];
       end
    
    endmodule
    blinking_led_child_slow.sv The LED_THREE blinks slower
    `timescale 1 ps / 1 ps
    `default_nettype none
    
    module blinking_led_child_slow (
    
       // clock
       input wire clock,
       input wire [31:0] counter,
    
       // Control signals for the LEDs
       output wire led_three_on
    );
    
       localparam COUNTER_TAP = 27;
       reg led_three_on_r;
    
       assign led_three_on = led_three_on_r;
       
       always_ff @(posedge clock) begin
          led_three_on_r   <= counter[COUNTER_TAP];
       end
    
    endmodule
    blinking_led_child_empty.sv The LED_THREE stays ON
    `timescale 1 ps / 1 ps
    `default_nettype none
    
    module blinking_led_child_empty (
    
       // clock
       input wire clock,
       input wire [31:0] counter,
    
       // Control signals for the LEDs
       output wire led_three_on
    
    );
    
       // LED is active low
       assign  led_three_on  = 1'b0;
    
    endmodule
    blinking_led_slow.sv The LED_TWO blinks slower.
    `timescale 1 ps / 1 ps
    `default_nettype none
    
    module blinking_led_slow(
    
       // clock
       input wire clock,
       input wire [31:0] counter,
       input wire reset,
    
       // Control signals for the LEDs
       output wire led_two_on,
       output wire led_three_on
    
    );
    
       localparam COUNTER_TAP = 27;
    
       reg led_two_on_r;
       assign  led_two_on    = led_two_on_r;
       
       // The counter:
       always_ff @(posedge clock) begin
             led_two_on_r <= counter[COUNTER_TAP];
       end
    
    
       blinking_led_child u_blinking_led_child(
             .led_three_on           (led_three_on),
             .counter             (counter),
             .clock                  (clock)
       );
    
    endmodule