eCPRI IP User Guide

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ID 683685
Date 9/19/2025
Public
Document Table of Contents
Document Table of Contents x
1. About the eCPRI IP 2. Getting Started 3. eCPRI IP Parameters 4. Functional Description 5. Interfaces 6. eCPRI IP Registers 7. eCPRI IP User Guide Archives 8. Document Revision History for the eCPRI IP User Guide
1. About the eCPRI IP x
1.1. eCPRI IP Features 1.2. eCPRI IP Device Family Support 1.3. eCPRI IP Device Speed Grade Support 1.4. eCPRI IP Resource Utilization 1.5. IP Verification 1.6. eCPRI IP Release Information
2. Getting Started x
2.1. Installing and Licensing the eCPRI IP 2.2. Specifying the eCPRI IP Parameters 2.3. eCPRI IP Generated File Structure 2.4. Simulating the eCPRI IP 2.5. Compiling the Full Design and Programming the FPGA
2.2. Specifying the eCPRI IP Parameters x
2.2.1. Reference and System PLL Clock for your IP Design
4. Functional Description x
4.1. High Level Data Path Flow 4.2. Operation of the eCPRI IP Blocks
4.1. High Level Data Path Flow x
4.1.1. Transmit TX Path 4.1.2. Receive RX Path 4.1.3. Supported Ethernet Variants
4.2. Operation of the eCPRI IP Blocks x
4.2.1. Packet Classifier 4.2.2. Ethernet Header Insertion/Removal 4.2.3. Concatenation/De-concatenation 4.2.4. Header Mapper/De-Mapper 4.2.5. eCPRI IWF Type 0 4.2.6. eCPRI Message 5 Packet Parser 4.2.7. Message Type 5 Flow 4.2.8. Packet Queue 4.2.9. eCPRI Message Type 4.2.10. Error Handling 4.2.11. RX Throttling
4.2.9. eCPRI Message Type x
4.2.9.1. eCPRI Message Type 0- IQ Data Transfer 4.2.9.2. eCPRI Message Type 1- Bit Sequence Transfer 4.2.9.3. eCPRI Message Type 2- Real Time Control Data 4.2.9.4. eCPRI Message Type 3- Generic Data Transfer 4.2.9.5. eCPRI Message Type 4- Remote Memory Access 4.2.9.6. eCPRI Message Type 5- One-Way Delay Measurement 4.2.9.7. eCPRI Message Type 6- Remote Reset 4.2.9.8. eCPRI Message Type 7- Event Indication 4.2.9.9. eCPRI Message Type 64- 255 Vendor Specific
5. Interfaces x
5.1. eCPRI IP Clock Signals 5.2. Power, Reset, and Firewalls Signals 5.3. TX Time of Day Interface 5.4. RX Time of Day Interface 5.5. Interrupt 5.6. Configuration Avalon® Memory-Mapped Interface 5.7. Ethernet MAC Source Interface 5.8. Ethernet MAC Sink Interface 5.9. External ST Source Interface 5.10. External ST Sink Interface 5.11. eCPRI IP Source Interface 5.12. eCPRI IP Sink Interface 5.13. Miscellaneous Interface Signals 5.14. IWF Type 0 eCPRI Interface 5.15. IWF Type 0 CPRI MAC Interface
5.2. Power, Reset, and Firewalls Signals x
5.2.1. Reset Control and Initialization Flows
5.7. Ethernet MAC Source Interface x
5.7.1. E-tile Hard IP for Ethernet 1588 PTP Signals 5.7.2. 25G Ethernet MAC 1588 PTP Signals 5.7.3. 10G Ethernet MAC 1588 PTP Signals 5.7.4. F-Tile Ethernet Hard IP 1588 PTP Signals 5.7.5. Agilex 5 Device Ethernet Hard IP 1588 PTP Signals
5.14. IWF Type 0 eCPRI Interface x
5.14.1. IWF Source Interface 5.14.2. IWF Sink Interface
5.15. IWF Type 0 CPRI MAC Interface x
5.15.1. CPRI 32-bit IQ Data TX Interface 5.15.2. CPRI 64-bit IQ Data TX Interface 5.15.3. CPRI 32-bit Ctrl_AxC TX Interface 5.15.4. CPRI 64-bit Ctrl_AxC TX Interface 5.15.5. CPRI 32-bit Vendor Specific TX Interface 5.15.6. CPRI 64-bit Vendor Specific TX Interface 5.15.7. CPRI 32-bit Real-time Vendor Specific TX Interface 5.15.8. CPRI 64-bit Real-time Vendor Specific TX Interface 5.15.9. CPRI Gigabit Media Independent Interface (GMII) 5.15.10. CPRI IP L1 Control and Status Interface
1. About the eCPRI IP
2. Getting Started
3. eCPRI IP Parameters
4. Functional Description
5. Interfaces
6. eCPRI IP Registers
7. eCPRI IP User Guide Archives
8. Document Revision History for the eCPRI IP User Guide

2.4. Simulating the eCPRI IP

You can simulate your eCPRI IP variation using any of the vendor-specific IEEE encrypted functional simulation models which are available in the <instance_name>/sim subdirectory of your project directory.

The eCPRI IP supports the Synopsys* VCS* , Synopsys* VCS* MX, Siemens* EDA QuestaSIM* , Aldec* Riviera-PRO* and Xcelium* Parallel simulators. The eCPRI IP generates a Verilog HDL and VHDL simulation model. The IP parameter editor offers you the option of generating a Verilog HDL or VHDL simulation model for the IP core. The IP design example also supports Verilog HDL/VHDL simulation model or testbench.

For more information about functional simulation models for IPs, refer to the Simulating FPGA Designs chapter in Quartus Prime Pro Edition User Guide: Third-party Simulation.

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