eCPRI IP User Guide

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ID 683685
Date 9/19/2025
Public
Document Table of Contents
Document Table of Contents x
1. About the eCPRI IP 2. Getting Started 3. eCPRI IP Parameters 4. Functional Description 5. Interfaces 6. eCPRI IP Registers 7. eCPRI IP User Guide Archives 8. Document Revision History for the eCPRI IP User Guide
1. About the eCPRI IP x
1.1. eCPRI IP Features 1.2. eCPRI IP Device Family Support 1.3. eCPRI IP Device Speed Grade Support 1.4. eCPRI IP Resource Utilization 1.5. IP Verification 1.6. eCPRI IP Release Information
2. Getting Started x
2.1. Installing and Licensing the eCPRI IP 2.2. Specifying the eCPRI IP Parameters 2.3. eCPRI IP Generated File Structure 2.4. Simulating the eCPRI IP 2.5. Compiling the Full Design and Programming the FPGA
2.2. Specifying the eCPRI IP Parameters x
2.2.1. Reference and System PLL Clock for your IP Design
4. Functional Description x
4.1. High Level Data Path Flow 4.2. Operation of the eCPRI IP Blocks
4.1. High Level Data Path Flow x
4.1.1. Transmit TX Path 4.1.2. Receive RX Path 4.1.3. Supported Ethernet Variants
4.2. Operation of the eCPRI IP Blocks x
4.2.1. Packet Classifier 4.2.2. Ethernet Header Insertion/Removal 4.2.3. Concatenation/De-concatenation 4.2.4. Header Mapper/De-Mapper 4.2.5. eCPRI IWF Type 0 4.2.6. eCPRI Message 5 Packet Parser 4.2.7. Message Type 5 Flow Remote Request Flow Request Flow Special Handling of Source and Destination MAC Address for Message Type 5 4.2.8. Packet Queue 4.2.9. eCPRI Message Type 4.2.10. Error Handling 4.2.11. RX Throttling
4.2.9. eCPRI Message Type x
4.2.9.1. eCPRI Message Type 0- IQ Data Transfer 4.2.9.2. eCPRI Message Type 1- Bit Sequence Transfer 4.2.9.3. eCPRI Message Type 2- Real Time Control Data 4.2.9.4. eCPRI Message Type 3- Generic Data Transfer 4.2.9.5. eCPRI Message Type 4- Remote Memory Access 4.2.9.6. eCPRI Message Type 5- One-Way Delay Measurement 4.2.9.7. eCPRI Message Type 6- Remote Reset 4.2.9.8. eCPRI Message Type 7- Event Indication 4.2.9.9. eCPRI Message Type 64- 255 Vendor Specific
5. Interfaces x
5.1. eCPRI IP Clock Signals 5.2. Power, Reset, and Firewalls Signals 5.3. TX Time of Day Interface 5.4. RX Time of Day Interface 5.5. Interrupt 5.6. Configuration Avalon® Memory-Mapped Interface 5.7. Ethernet MAC Source Interface 5.8. Ethernet MAC Sink Interface 5.9. External ST Source Interface 5.10. External ST Sink Interface 5.11. eCPRI IP Source Interface 5.12. eCPRI IP Sink Interface 5.13. Miscellaneous Interface Signals 5.14. IWF Type 0 eCPRI Interface 5.15. IWF Type 0 CPRI MAC Interface
5.2. Power, Reset, and Firewalls Signals x
5.2.1. Reset Control and Initialization Flows
5.7. Ethernet MAC Source Interface x
5.7.1. E-tile Hard IP for Ethernet 1588 PTP Signals 5.7.2. 25G Ethernet MAC 1588 PTP Signals 5.7.3. 10G Ethernet MAC 1588 PTP Signals 5.7.4. F-Tile Ethernet Hard IP 1588 PTP Signals 5.7.5. Agilex 5 Device Ethernet Hard IP 1588 PTP Signals
5.14. IWF Type 0 eCPRI Interface x
5.14.1. IWF Source Interface 5.14.2. IWF Sink Interface
5.15. IWF Type 0 CPRI MAC Interface x
5.15.1. CPRI 32-bit IQ Data TX Interface 5.15.2. CPRI 64-bit IQ Data TX Interface 5.15.3. CPRI 32-bit Ctrl_AxC TX Interface 5.15.4. CPRI 64-bit Ctrl_AxC TX Interface 5.15.5. CPRI 32-bit Vendor Specific TX Interface 5.15.6. CPRI 64-bit Vendor Specific TX Interface 5.15.7. CPRI 32-bit Real-time Vendor Specific TX Interface 5.15.8. CPRI 64-bit Real-time Vendor Specific TX Interface 5.15.9. CPRI Gigabit Media Independent Interface (GMII) 5.15.10. CPRI IP L1 Control and Status Interface
1. About the eCPRI IP
2. Getting Started
3. eCPRI IP Parameters
4. Functional Description
5. Interfaces
6. eCPRI IP Registers
7. eCPRI IP User Guide Archives
8. Document Revision History for the eCPRI IP User Guide

4.2.7. Message Type 5 Flow

The one-way delay measurement process uses hardware-assisted timestamping via eCPRI message type 5.

The IP offers two measurement flows:

  • Remote request flow - initiated by host, measured at target
  • Request flow - initiated and measured at host

Remote Request Flow

Figure 11. Software Initiated Hardware Assisted One-Way Measurement Remote Request Flow

In the remote request flow:

  1. The CPU programs the measurement ID, remote equest, and start bits in the eCPRI Message 5 control register to initiate the one-way delay measurement process.
  2. The eCPRI message 5 packet parser sends the remote request packet to the PHY.
  3. The FPGA hosting the target receives the remote request packet.
  4. In the one-step mechanism, the FPGA hosting the target generates timestamp T1 based on time-of-day on receiving the remote request packet. The parser then forwards the Request packet to MAC or PHY, and the PTP hardware inserts the compensation value CV1 into the packet.
  5. In the two-step mechanism, the target's packet parser generates timestamp T1 before sending the request packet to PHY and stores timestamp T1 in the FIFO.
  6. The target checks for valid FIFO entry via a polling mechanism. If a valid entry is present, it reads the entry to obtain timestamp T1. In system diagrams, dotted arrows on the host side indicate the blocks involved in the two-step mechanism.
  7. The host parser sends a request with follow-up message containing timestamp T1, which refers to the request packet sent in step 5.
  8. The FPGA hosting the host receives the request packet, and the receiving MAC generates timestamp T2.
  9. In the one-step mechanism, the parser receives the request packet and collects timestamp T1 from the received packet. It then calculates the compensation value CV2 based on timestamp T2 generated between the MAC and the parser.
  10. In the two-step mechanism, the parser acting as the host collects timestamp T1 from the request with follow-up message sent in step 7. It then calculates the compensation value CV2 based on timestamp T2 generated between the MAC and the parser.
  11. After decoding the eCPRI packet, the packet parser sends a response packet containing timestamp T2 and the calculated compensation value CV2 to the MAC block.
  12. The FPGA hosting the target clock receives the Response packet, and the receiving MAC generates timestamp T2.
  13. With all four values — T1, T2, CV1, and CV2 — available, the target stack calculates the final one-way delay.

Request Flow

Figure 12. Software Initiated HW Assisted One Way Measurement Request Flow
  1. The CPU program sets the measurement ID, remote request, and start bits in the eCPRI message 5 control register to initiate the one-way delay measurement process.
  2. In the one-step mechanism, the FPGA hosting the host generates timestamp T1 based on the time-of-day output for the request packet. The parser then sends the request packet to the MAC or PHY, and the PTP hardware inserts the compensation value CV1 into the packet.
  3. In the two-step mechanism, the packet parser generates timestamp T1 before sending the request packet to the PHY and stores this timestamp in the FIFO.
  4. The parser checks for a valid entry in the FIFO via a polling mechanism. If a valid entry is found, it reads the entry to retrieve timestamp T1. In diagrams, dotted arrows on the host side indicate the blocks involved in the 2-step mechanism.
  5. The parser sends a Request with Follow-up message containing timestamp T1, referring to the Request packet sent in Step 3.
  6. The FPGA hosting the target receives the request packet, and the receiving MAC generates timestamp T2.
  7. In the one-step mechanism, the parser receives the Request packet and extracts timestamp T1 from the received packet. It then calculates the compensation value CV2 based on timestamp T2 generated between the MAC and the parser.
  8. In the two-step mechanism, the target parser obtains timestamp T1 from the request with follow-up message sent in Step 5. It then calculates the compensation value CV2 based on timestamp T2 generated between the MAC and the parser.
  9. After decoding the eCPRI packet, the packet parser sends a Response packet containing timestamp T2 and the calculated compensation value CV2 to the MAC block.
  10. The FPGA hosting the host clock receives the Response packet containing timestamp T2.
  11. With T1, T2, CV1, and CV2 available, the host parser calculates the final one-way delay value.

Special Handling of Source and Destination MAC Address for Message Type 5

For FPGA devices initiating a one-way delay measurement, special handling applies to message type 5. When the FPGA sends the first message Type 5 to start the measurement using the same source and destination MAC address and VLAN tag as other messages.

Table 19.   MAC Address and VLAN for One-way Delay Measurement Remote Request
Step Description Action Type MAC Destination Address VLAN Device
2 Remote Request 0x03 User Specify Host
4 Request 0x00 Source Address from step 2 From step 2 Target
11 Response 0x02 Source Address rom step 4 From step 2 Host

For all subsequent messages in the one-way delay measurement process, the FPGA must swap the source and destination MAC addresses for the returning messages. If the incoming packet contains a VLAN tag, the same VLAN tag is included in the return packet. If the incoming packet does not have a VLAN tag, no VLAN tag is added in the return packet, overriding the device’s VLAN setting.

Table 20.   MAC Address and VLAN for Remote Request with Follow Up
Step Description Action Type MAC Destination Address VLAN Device
2 Remote Request/Follow_Up 0x04 User Specify Host
4 Request with Follow_Up 0x01 Source Address from step 2 From step 2 Target
7 Follow_Up 0x05 Target
11 Response 0x02 Source Address from step 7 From step 7 Host
Table 21.  MAC Address and VLAN for One-way Delay Measurement Request
Step Description Action Type MAC Destination Address VLAN Device
2 Request 0x00 User Specify Host
9 Response 0x02 Source address from step 2 From step 2 Target
Table 22.   MAC Address and VLAN for Request with Follow Up
Step Description Action Type MAC Destination Address VLAN Device
2 Request/Follow_Up 0x01 User specify Host
5 Follow_Up 0x05 User specify Host
9 Response 0x02 Source address from step 5 From step 2 Target
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