2023.11.17 |
23.3 |
3.0.0 |
- Updated the eCPRI Intel FPGA IP Core Device Family Support table.
- Updated the Device Speed Grade Support table.
- Updated the Parameters: Configuration Tab table.
- Updated the eCPRI Intel FPGA IP High-Level System Overview diagram.
- Updated the Signals of the E-tile Hard IP for Ethernet 1588 PTP Interface table.
- Updated the Signals of the 25G Ethernet MAC 1588 PTP table.
- Updated the Signals of the 10G Ethernet MAC 1588 PTP table.
- Updated the Signals of the External ST Sink Interface table.
- Miscellaneous text changes throughout the document.
|
2023.08.03 |
23.2 |
2.0.4 |
- Updated the register map.
- Corrected typos in the eCPRI IP Reset, Power, and Firewalls Signals table.
|
2023.05.19 |
23.1 |
2.0.3 |
- In the IP Parameters chapter, updated the description for the Advance Mapping Mode parameter in the Parameters: Configuration Tab table.
- Updated product family name to "Intel Agilex 7"
|
2023.02.24 |
22.4 |
2.0.2 |
Bug fixes |
2022.11.15 |
22.3 |
2.0.1 |
- Updated the Device Speed Grade Support.
- Updated the Resource Utilization.
|
2022.08.26 |
22.2 |
2.0.0 |
- Added information about the packets arbitration scheme in section: Transmit TX Path.
- Added information about the Data Flow Identification in section: Receive RX Path.
- Added new IP parameters:
- Default VLAN ID
- Data Flow Identification
- Packets Arbitration Scheme
- TX Packets Default Priority
- TX Arbitration Queue 0 Depth
- TX Arbitration Queue 1 Depth
- TX Arbitration Queue 2 Depth
- TX Arbitration Queue 3 Depth
- TX Arbitration Queue 4 Depth
- TX Arbitration Queue 5 Depth
- TX Arbitration Queue 6 Depth
- TX Arbitration Queue 7 Depth
- Added new signals:
- tx_queue_<N>_fifo_full
- ext_source_pkt_type
- ext_tx_ingress_timestamp_96b_data
- ptp_tx_ingress_timestamp_96b_data
- Added a new register eCPRI ORAN C/U Plane VLAN ID Match in section: IP Registers.
|
2022.07.01 |
22.1 |
1.4.1 |
- Corrected the I/O direction for the following signals:
- avst_source_sop
- avst_source_eop
- avst_source_empty
- Corrected the signal name to which signals of the eCPRI IP Source and Sink Interface are synchronized.
- Corrected the figure: eCPRI IP Core Reset Logic.
- Added support for QuestaSim* simulator.
- Removed support for ModelSim* SE simulator.
|
2021.12.14 |
21.3 |
1.4.1 |
- Corrected the signal descriptions for Configuration Avalon® Memory-Mapped Interface .
- Corrected the register descriptions for Ethertype Register and UDP Port Register.
- Corrected IP version for Intel® Quartus® Prime software version 21.2.
|
2021.11.11 |
21.2 |
1.4.0 |
Clarified information about the streaming mode in section: eCPRI IP Sink Interface and IP Parameters. |
2021.10.01 |
21.2 |
1.4.0 |
- Added support for Intel® Agilex™ 7 F-tile devices.
- Added support for multi-channel designs. For more information, refer to the eCPRI Intel FPGA IP Design Example User Guide.
- Removed support for NCSim.
|
2021.02.26 |
20.4 |
1.3.0 |
- Added support for Intel® Agilex™ 7 E-tile devices.
- Updated the following signal descriptions:
- tx_egress_timestamp_96b_fingerprint
- ptp_timestamp_request_fingerprint
- Added the following signals in section External ST Sink Interface:
- ext_ptp_timestamp_request_fingerprint
- ext_tx_egress_timestamp_96b_fingerprint
|
2021.01.08 |
20.3 |
1.2.0 |
- The IP now supports interworking function (IWF) type 0.
- Supports pairing of eCPRI Intel FPGA IP with O-RAN Intel FPGA IP.
- Updated resource utilization numbers for IWF in Resource Utilization section.
- Updated Table: eCPRI Intel FPGA IP Core Release Information for 20.3 release.
- Updated Figure: eCPRI IP Parameter Editor with new parameters.
- Updated Parameter Settings section.
- Added following new interfaces in section Interfaces:
- IWF Type 0 eCPRI Source Interface
- IWF Type 0 eCPRI Sink Interface
- IWF Type 0 CPRI MAC Interface
- Updated Figure: eCPRI Intel FPGA IP High-Level System Overview.
- Added description for two new blocks in section Operation of the eCPRI IP Blocks:
- Added IWF related new clock signals in section eCPRI IP Input Clocks.
- Added following reset signals in Table: eCPRI IP Reset, Power, and Firewalls Signals.
- Created following new sections to document IWF Type 0 related signals:
- IWF Type 0 eCPRI Interface
- IWF Type 0 eCPRI MAC Interface
- Corrected one field in Table: eCPRI Common Header Format.
|
2020.05.19 |
20.1 |
1.1.0 |
- Added support for Intel® Arria® 10 devices.
- The IP now supports 10G data rate with Intel® Stratix® 10 and Intel® Arria® 10 devices.
- IP supports streaming of Ethernet frame size up to 9,000 bytes.
- Added new Table: eCPRI Intel FPGA IP Feature Matrix in section Supported Features.
- Updated resource utilization numbers in Table: Resource Utilization.
- Added following new parameters in Table: Parameters: Configuration Tab:
- Streaming
- Pair with ORAN
- One-way Delay Measurement Timer Bit-width
- Remote Memory Access Timer Bit-width
- Remote Reset Timer Bit-width
- Modified Figure: eCPRI Intel FPGA IP High-Level System Overview to include client logic.
- Updated Section: Supported Ethernet Variants.
- Updated Section: Error Handling.
- Added new signals in the following:
- Table: eCPRI IP Input Clocks
- Table: Signals of the TX Time of Day Interface
- Table: Signals of the External ST Sink Interface
- Table: Signals of the eCPRI IP Sink Interface
- Added new Table: Miscellaneous Interface Signals.
- Updated the following register tables:
- Table: eCPRI Version Register at Offset 0x000
- Table: eCPRI TX Error Message Register at Offset 0x0004
- Table: eCPRI RX Error Message Register at Offset 0x0005
- Table: eCPRI Error Mask Message Register at Offset 0x0006
- Table: RX Error Register at Offset 0x003E
|
2020.04.15 |
19.4 |
1.0.0 |
Corrected information in Table: eCPRI Version Register at Offset 0x000. |
2020.04.13 |
19.4 |
1.0.0 |
Initial release. |