eCPRI Intel® FPGA IP User Guide

ID 683685
Date 11/15/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

5.2. Power, Reset, and Firewalls Signals

Table 27.  eCPRI IP Reset, Power, and Firewalls SignalsThese signals are asynchronous.
Signal Name Width (Bits) I/O Direction Description
rst_tx_n 1 Input Reset signal from Ethernet MAC TX.

Resets the eCPRI IP in RX direction. Resets the De-concatenation, Header mapper/De-mapper, Ethernet header removal, eCPRI message 5 packet parser and, Packet classifier.

rst_rx_n 1 Input Reset signal from Ethernet MAC RX.

Resets the eCPRI IP in TX direction. Resets the Concatenation, Header mapper/De-mapper, Ethernet header insertion, eCPRI message 5 packet parser, and Packet queue.

rst_csr_n 1 Input Reset signal for CSR logic.

Resets the eCPRI IP control and status registers. When asserted, resets the eCPRI IP.

tx_lanes_stable 1 Input Signal that indicates the clk_tx signal from MAC is stable and ready for operation.
rx_pcs_ready 1 Input Signal that indicates the clk_rx signal from MAC is stable and ready for operation.
iwf_rst_tx_n 1 Input Reset signal for the IWF TX path.
iwf_rst_rx_n 1 Input Reset signal for the IWF RX path.
rst_tx_n_sync 1 Output

Reset output from IWF. This signal is synchronous to clk_tx.

Intel recommends you to connect this signal to iwf_rst_tx_n.
rst_rx_n_sync 1 Output

Reset output from IWF. This signal is synchronous to clk_rx.

Intel recommends you to connect this signal to iwf_rst_rx_n.
iwf_gmii_rxreset_n[N] 1 Input Resets the GMII receiver interface and FIFO read logic.
iwf_gmii_txreset_n[N] 1 Input Resets the GMII transmitter interface and FIFO write logic.
gmii_rxreset_n[N] 1 Output Resets the GMII receiver interface and FIFO read logic.
gmii_txreset_n[N] 1 Output Resets the GMII transmitter interface and FIFO write logic.