eCPRI Intel® FPGA IP User Guide

ID 683685
Date 11/15/2022

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5.8. Ethernet MAC Sink Interface

Table 36.  Signals of the 25G Ethernet MAC Sink Interface This section lists port from 25G Ethernet MAC to eCPRI IP . All signals are synchronous to mac_clk_rx.
Signal Name Width (Bits) I/O Direction Description
mac_sink_valid 1 Input Indicates Avalon® source valid from Ethernet to MAC eCPRI.
mac_sink_data DATA_WIDTH 5 Input Indicates Avalon® source write data from Ethernet MAC to eCPRI.
mac_sink_sop 1 Input Indicates Avalon® sink start of packet (SOP) from Ethernet MAC to eCPRI. Indicate the beginning of packet.
mac_sink_eop 1 Input Avalon® source end of packet (EOP) from Ethernet MAC to eCPRI. Indicate the end of packet.
mac_sink_empty LOG2(DATA_WIDTH5/8) Input Avalon® source empty from Ethernet MAC to eCPRI. Indicates the number of symbols that are empty, that is, do not represent valid data.
mac_sink_ready 1 Output Avalon® sink ready driven from Ethernet MAC. Indicate eCPRI can accept data.
mac_sink_error 6 Input Avalon® sink error from Ethernet MAC to eCPRI. A bit mask to mark errors affecting the data being transferred in the current cycle.
5 This is set to 64. This parameter is hidden from user and you can't change it.