eCPRI Intel® FPGA IP User Guide

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ID 683685
Date 7/01/2022
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Getting Started 3. IP Parameters 4. Functional Description 5. Interface Overview 6. IP Registers 7. eCPRI Intel FPGA IP User Guide Archives 8. Document Revision History for eCPRI Intel® FPGA IP User Guide
1. Introduction x
1.1. Supported Features 1.2. Device Family Support 1.3. eCPRI Intel® FPGA IP Device Speed Grade Support 1.4. Resource Utilization 1.5. Intel® FPGA IP Core Verification 1.6. Release Information
2. Getting Started x
2.1. Installing and Licensing 2.2. Specifying the IP Core Parameters and Options 2.3. Generated File Structure 2.4. Simulating the IP Core 2.5. Compiling the Full Design and Programming the FPGA
2.2. Specifying the IP Core Parameters and Options x
2.2.1. Reference and System PLL Clock for your IP Design
4. Functional Description x
4.1. Interfaces 4.2. High Level Data Path Flow 4.3. Operation of the eCPRI IP Blocks
4.2. High Level Data Path Flow x
4.2.1. Transmit TX Path 4.2.2. Receive RX Path 4.2.3. Supported Ethernet Variants
4.3. Operation of the eCPRI IP Blocks x
4.3.1. Packet Classifier 4.3.2. Ethernet Header Insertion/Removal 4.3.3. Concatenation/De-concatenation 4.3.4. Header Mapper/De-Mapper 4.3.5. eCPRI IWF Type 0 4.3.6. eCPRI Message 5 Packet Parser 4.3.7. Packet Queue 4.3.8. eCPRI Message Type 4.3.9. Error Handling 4.3.10. RX Throttling
4.3.8. eCPRI Message Type x
4.3.8.1. eCPRI Message Type 0- IQ Data Transfer 4.3.8.2. eCPRI Message Type 1- Bit Sequence Transfer 4.3.8.3. eCPRI Message Type 2- Real Time Control Data 4.3.8.4. eCPRI Message Type 3- Generic Data Transfer 4.3.8.5. eCPRI Message Type 4- Remote Memory Access 4.3.8.6. eCPRI Message Type 5- One-Way Delay Measurement 4.3.8.7. eCPRI Message Type 6- Remote Reset 4.3.8.8. eCPRI Message Type 7- Event Indication 4.3.8.9. eCPRI Message Type 64- 255 Vendor Specific
5. Interface Overview x
5.1. Clock Signals 5.2. Power, Reset, and Firewalls Signals 5.3. TX Time of Day Interface 5.4. RX Time of Day Interface 5.5. Interrupt 5.6. Configuration Avalon® Memory-Mapped Interface 5.7. Ethernet MAC Source Interface 5.8. Ethernet MAC Sink Interface 5.9. External ST Source Interface 5.10. External ST Sink Interface 5.11. eCPRI IP Source Interface 5.12. eCPRI IP Sink Interface 5.13. Miscellaneous Interface Signals 5.14. IWF Type 0 eCPRI Interface 5.15. IWF Type 0 CPRI MAC Interface
5.2. Power, Reset, and Firewalls Signals x
5.2.1. Reset Control and Initialization Flows
5.7. Ethernet MAC Source Interface x
5.7.1. E-tile Hard IP for Ethernet 1588 PTP Signals 5.7.2. 25G Ethernet MAC 1588 PTP Signals 5.7.3. 10G Ethernet MAC 1588 PTP Signals
5.14. IWF Type 0 eCPRI Interface x
5.14.1. IWF Source Interface 5.14.2. IWF Sink Interface
5.15. IWF Type 0 CPRI MAC Interface x
5.15.1. CPRI 32-bit IQ Data TX Interface 5.15.2. CPRI 64-bit IQ Data TX Interface 5.15.3. CPRI 32-bit Ctrl_AxC TX Interface 5.15.4. CPRI 64-bit Ctrl_AxC TX Interface 5.15.5. CPRI 32-bit Vendor Specific TX Interface 5.15.6. CPRI 64-bit Vendor Specific TX Interface 5.15.7. CPRI 32-bit Real-time Vendor Specific TX Interface 5.15.8. CPRI 64-bit Real-time Vendor Specific TX Interface 5.15.9. CPRI Gigabit Media Independent Interface (GMII) 5.15.10. CPRI IP L1 Control and Status Interface
1. Introduction
2. Getting Started
3. IP Parameters
4. Functional Description
5. Interface Overview
6. IP Registers
7. eCPRI Intel FPGA IP User Guide Archives
8. Document Revision History for eCPRI Intel® FPGA IP User Guide

8. Document Revision History for eCPRI Intel® FPGA IP User Guide

Document Version Intel® Quartus® Prime Software Version IP Version Changes
2022.07.01 22.1 1.4.1
  • Corrected the I/O direction for the following signals:
    • avst_source_sop
    • avst_source_eop
    • avst_source_empty
  • Corrected the signal name to which signals of the eCPRI IP Source and Sink Interface are synchronized.
  • Corrected the figure: eCPRI IP Core Reset Logic.
  • Added support for QuestaSim* simulator.
  • Removed support for ModelSim* SE simulator.
2021.12.14 21.3 1.4.1
  • Corrected the signal descriptions for Configuration Avalon® Memory-Mapped Interface .
  • Corrected the register descriptions for Ethertype Register and UDP Port Register.
  • Corrected IP version for Intel® Quartus® Prime software version 21.2.
2021.11.11 21.2 1.4.0 Clarified information about the streaming mode in section: eCPRI IP Sink Interface and IP Parameters.
2021.10.01 21.2 1.4.0
  • Added support for Intel® Agilex™ F-tile devices.
  • Added support for multi-channel designs. For more information, refer to the eCPRI Intel FPGA IP Design Example User Guide.
  • Removed support for NCSim.
2021.02.26 20.4 1.3.0
  • Added support for Intel® Agilex™ E-tile devices.
  • Updated the following signal descriptions:
    • tx_egress_timestamp_96b_fingerprint
    • ptp_timestamp_request_fingerprint
  • Added the following signals in section External ST Sink Interface:
    • ext_ptp_timestamp_request_fingerprint
    • ext_tx_egress_timestamp_96b_fingerprint
2021.01.08 20.3 1.2.0
  • The IP now supports interworking function (IWF) type 0.
  • Supports pairing of eCPRI Intel FPGA IP with O-RAN Intel FPGA IP.
  • Updated resource utilization numbers for IWF in Resource Utilization section.
  • Updated Table: eCPRI Intel FPGA IP Core Release Information for 20.3 release.
  • Updated Figure: eCPRI IP Parameter Editor with new parameters.
  • Updated Parameter Settings section.
  • Added following new interfaces in section Interfaces:
    • IWF Type 0 eCPRI Source Interface
    • IWF Type 0 eCPRI Sink Interface
    • IWF Type 0 CPRI MAC Interface
  • Updated Figure: eCPRI Intel FPGA IP High-Level System Overview.
  • Added description for two new blocks in section Operation of the eCPRI IP Blocks:
    • eCPRI IWF Type 0
  • Added IWF related new clock signals in section eCPRI IP Input Clocks.
  • Added following reset signals in Table: eCPRI IP Reset, Power, and Firewalls Signals.
  • Created following new sections to document IWF Type 0 related signals:
    • IWF Type 0 eCPRI Interface
    • IWF Type 0 eCPRI MAC Interface
  • Corrected one field in Table: eCPRI Common Header Format.
2020.05.19 20.1 1.1.0
  • Added support for Intel® Arria® 10 devices.
  • The IP now supports 10G data rate with Intel® Stratix® 10 and Intel® Arria® 10 devices.
  • IP supports streaming of Ethernet frame size up to 9,000 bytes.
  • Added new Table: eCPRI Intel FPGA IP Feature Matrix in section Supported Features.
  • Updated resource utilization numbers in Table: Resource Utilization.
  • Added following new parameters in Table: Parameters: Configuration Tab:
    • Streaming
    • Pair with ORAN
    • One-way Delay Measurement Timer Bit-width
    • Remote Memory Access Timer Bit-width
    • Remote Reset Timer Bit-width
  • Modified Figure: eCPRI Intel FPGA IP High-Level System Overview to include client logic.
  • Updated Section: Supported Ethernet Variants.
  • Updated Section: Error Handling.
  • Added new signals in the following:
    • Table: eCPRI IP Input Clocks
    • Table: Signals of the TX Time of Day Interface
    • Table: Signals of the External ST Sink Interface
    • Table: Signals of the eCPRI IP Sink Interface
  • Added new Table: Miscellaneous Interface Signals.
  • Updated the following register tables:
    • Table: eCPRI Version Register at Offset 0x000
    • Table: eCPRI TX Error Message Register at Offset 0x0004
    • Table: eCPRI RX Error Message Register at Offset 0x0005
    • Table: eCPRI Error Mask Message Register at Offset 0x0006
    • Table: RX Error Register at Offset 0x003E
2020.04.15 19.4 1.0.0 Corrected information in Table: eCPRI Version Register at Offset 0x000.
2020.04.13 19.4 1.0.0 Initial release.
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