AN 509: Multiplexing SDIO Devices Using Altera MAX Series

ID 683683
Date 9/22/2014

1.2. I2C Select Line Multiplexer Using MAX II Devices

The detailed description of the implementation is based on the MAX II devices. This application can also be implemented in MAX V and MAX 10 devices.

The “MUX” in Figure 1 represents a unidirectional multiplexer that is implemented using a MAX II device. The select line for the multiplexer is controlled through an I2C interface, which is also implemented in the same device. The multiplexer is thus an I2C slave, and the clock line from the host controller is either connected to the SD Device A or the SD Device B, depending on the I2C data received.

Figure 2.  I2C Select Line MUX Implementation in a MAX II Device

The I2C interface implementation in the MAX II device (I2C slave) has a 7-bit address and follows the general I2C protocol. The start signal is sent by the master, followed by the 7-bit address and an R/W bit. When the address broadcast on the I2C bus matches with the slave device’s address, an ACK (acknowledge) signal is sent by the device. This is followed by a DATA byte, as per the select line selection that is required by the master. This is then followed by another ACK signal by the slave. The end of a session of data transaction is when the Stop (P) signal is sent by the master.

Table 1.   I2C Interface Pin Description
Signal Purpose Direction
SCL I2C Clock Output
SDA I2C Serial Data Bidirectional
Figure 3.  I2C Signal Format

This design example can be implemented with the EPM240G or EPM240 device or any other MAX II device. It is demonstrated in an I2C bus environment. Implementation involves using this design example source code and allocating I2C bus lines, the SD host controller clock line, the eject line, and the clock lines for the SD Device A and SD Device B. An LED indicator that is used to indicate the current selection is connected to an output port assigned to display the select line status. This SD multiplexer is demonstrated on the MDN-B2 demo board and with the help of an I2C simulator. The simulator is created using a PC parallel port and interfacing hardware to create an I2C-compliant two-wire bus. The MDN-B2 features two SD sockets to accommodate two SD devices (to be multiplexed) and an SD card-shaped PCB adapter that fits into a standard SD socket of an SD host.

The utility program, which uses the parallel port, and its hardware interface with the MAX II-based multiplexer and provide the SDA and SCL connections as required on an I2C two-wire system. When implemented, this design allows the I2C master (or the control panel of the Maxim utility) to control the select line of the MAX II-based multiplexer on the MDN-B2. The following table lists the EPM240G pin assignments for this design example.

Table 2.  EPM240G Pin Assignments for Design Example Using the MDN-B2 Demo BoardAssign unused pins As input-tristated in the Quartus® II software. You must also enable the Auto Open-Drain setting on the SCLK and SDA pins. To do this, on the Assignments menu, click Settings and then select Analysis and Synthesis Settings to enable the Auto Open-Drain setting. These settings are followed by a compilation cycle.
Signal Pin Signal Pin
APD_inhibit Pin 14 APD_inhibit_inv Pin 12
eject Pin 64 SCLK Pin 39
SDA Pin 40 sdA_clock Pin 2
sdB_clock Pin 7 sd_host_clock Pin 28
sel Pin 76