Intel® High Level Synthesis Compiler Pro Edition: Getting Started Guide

Download
ID 683680
Date 3/28/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

2.1. Running an Intel® HLS Compiler Design Example (Linux)

To run an Intel® HLS Compiler design example on Linux systems:

  1. Start a terminal session and initialize the Intel® HLS Compiler environment.
    For instructions how to initialize the environment, see Initializing the Intel HLS Compiler Pro Edition Environment.
  2. Navigate to the <quartus_installdir>/hls/examples/<design_example_name> directory, where <quartus_installdir> is the directory where you installed Intel® Quartus® Prime software.
    For example, /home/<username>/intelFPGA_pro/22.1 .
  3. Run the make test-x86-64 command. This command compiles the C++ source code to an x86-64 binary executable. Then, run the generated executable on your CPU.
    Expected outcome after you run the make test-x86-64 command:
    • The console displays the command used to generate the binary. For example, i++ -march=x86-64 -o test-x86-64 <source_files> .
    • The HLS compiler creates an executable file (for example, test-x86-64) in the current working directory.
    • The console displays the output of the executable to signify a successful execution.
    $ make test-x86-64
    i++ MGS.cpp QRD_Testbench.cpp TestbenchHelpers.cpp  -ffp-contract=fast -ffp-reassociate -march=x86-64 -o test-x86-64
    +----------------------------------------+
    | Run ./test-x86-64 to execute the test. |
    +----------------------------------------+
  4. Run the make test-fpga command. The command compiles the C++ source code to a hardware executable and then runs a simulation of the generated HDL.
    Expected outcome after you run the make test-fpga command:
    • The console displays the command it uses to generate the testbench binary and the contents of the project directory. For example, i++ -march="<FPGA_family_or_part_number>" <source_files> -o test-fpga.
    • The HLS compiler creates a .prj directory (for example, test-fpga.prj) in the current working directory.
    • The console displays the output of the executable to signify a successful execution.
    $ make test-fpga
    i++ MGS.cpp QRD_Testbench.cpp TestbenchHelpers.cpp  -v -ffp-contract=fast -ffp-reassociate -march=Arria10 -o test-fpga
    Target FPGA part name:   10AX115U1F45I1SG
    Target FPGA family name: Arria 10
    Target FPGA speed grade: -2
    Analyzing MGS.cpp for testbench generation
    Creating x86-64 testbench 
    Analyzing MGS.cpp for hardware generation
    Analyzing QRD_Testbench.cpp for testbench generation
    Creating x86-64 testbench 
    Analyzing QRD_Testbench.cpp for hardware generation
    Analyzing TestbenchHelpers.cpp for testbench generation
    Creating x86-64 testbench 
    Analyzing TestbenchHelpers.cpp for hardware generation
    Optimizing component(s) and generating Verilog files
    Generating cosimulation support
    Generating simulation files for components: qrd
    HLS simulation directory: /data/username/HLS_Trainings/examples/QRD/test-fpga.prj/verification.
    Linking x86 objects
    +--------------------------------------+
    | Run ./test-fpga to execute the test. |
    +--------------------------------------+

Did you find the information on this page useful?

Characters remaining:

Feedback Message