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1.1. 5G LDPC-V Intel® FPGA IP Features
- 3GPP 5G LDPC specification compliant
- For the transmitter:
- CRC checker module (CRC24B without concatenation)
- Rate matcher
- Per-block modifiable code block length and code rate
- For the receiver:
- Improved block-error rate (BLER) performance for high reliability signal-to-noise ratios (SNRs) for ultra reliable low-latency communications (URLLC)
- 5 bits or 6 bits LLR input width
- Derate matcher
- Bypassable hybrid automatic repeat request (HARQ) block
- Code block segmentation CRC module (CRC24B without concatenation)
- Per-block modifiable code block length, code rate, and maximum number of iterations
- Configurable input precision
- Layered decoder scheduling architecture to double the speed of convergence compared to non-layered architecture
- Early termination based on the syndrome check using four layers or full syndrome after each iteration.
- No external memory requirement
- Bit-accurate C models and MATLAB models for performance simulation
- Verilog HDL testbench option
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