Low Latency 40G Ethernet Intel® FPGA IP Release Notes

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ID 683651
Date 11/25/2024
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Document Table of Contents x
1. Low Latency 40G Ethernet Intel® FPGA IP Release Notes
1. Low Latency 40G Ethernet Intel® FPGA IP Release Notes x
1.1. Low Latency 40G Ethernet Intel® FPGA IP (intel_eth_e40) v4.0.0 1.2. Low Latency 40G Ethernet Intel® FPGA IP (intel_eth_e40) v3.0.0 1.3. Low Latency 40G Ethernet Intel® FPGA IP (intel_eth_e40) v1.0.0 1.4. Low Latency 40G Ethernet IP Core (alt_e40) v19.2.0 1.5. Low Latency 40G Ethernet IP Core (alt_e40) v17.1
1. Low Latency 40G Ethernet Intel® FPGA IP Release Notes

1.2. Low Latency 40G Ethernet Intel® FPGA IP (intel_eth_e40) v3.0.0

Table 2.  v3.0.0 2024.07.08
Quartus® Prime Version Description Impact
24.2
  • Added Analog Parameters tab in the IP GUI.
  • Added the Enable cdr dedicated clk option in the IP GUI.
  • Added support for Agilex™ 5 D-Series FPGAs.1
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1 Device support for Agilex™ 5 D-Series FPGAs and SoCs in the Quartus® Prime Pro Edition software version 24.2 is restricted. To enable D-Series device support in your instance of the Quartus® Prime Pro Edition software, contact your regional Altera sales representative.
Level Two Title