Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs 1.1 Errata

Download PDF
ID 683650
Date 8/06/2018
Public
Document Table of Contents
Document Table of Contents x
Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs 1.1 Errata
Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs 1.1 Errata x
Flash Fallback Does Not Meet PCIe Timeout Unsupported Transaction Layer Packet Types Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs 1.1 Errata Revision History
Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs 1.1 Errata

Unsupported Transaction Layer Packet Types

Description

The Acceleration Stack FPGA Interface Manager (FIM) does not support PCIe* Memory Read Lock, Configuration Read Type 1, and Configuration Write Type 1 transaction layer packets (TLPs). If the device receives a PCIe* packet of this type, it does not respond with a Completion packet as expected.

Workaround

No workaround available.

Status

Affects: Intel® Acceleration Stack 1.0 Production and 1.1 Production

Status: No planned fix

Level Two Title