Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs 1.1 Errata

ID 683650
Date 8/06/2018

Unsupported Transaction Layer Packet Types


The Acceleration Stack FPGA Interface Manager (FIM) does not support PCIe* Memory Read Lock, Configuration Read Type 1, and Configuration Write Type 1 transaction layer packets (TLPs). If the device receives a PCIe* packet of this type, it does not respond with a Completion packet as expected.


No workaround available.


Affects: Intel® Acceleration Stack 1.0 Production and 1.1 Production

Status: No planned fix