Nios® V Processor Reference Manual

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ID 683632
Date 10/07/2024
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Document Table of Contents
Document Table of Contents x
1. Overview 2. Nios® V/c Processor 3. Nios® V/m Processor 4. Nios® V/g Processor 5. Nios V Processor Reference Manual Archives 6. Document Revision History for the Nios® V Processor Reference Manual
1. Overview x
1.1. Quartus® Prime Software Support
2. Nios® V/c Processor x
2.1. Processor Performance Benchmarks 2.2. Processor Pipeline 2.3. Processor Architecture 2.4. Programming Model 2.5. Core Implementation
2.3. Processor Architecture x
2.3.1. General-Purpose Register File 2.3.2. Arithmetic Logic Unit 2.3.3. Reset and Debug Signals 2.3.4. Memory and I/O Organization 2.3.5. Error Correction Code (ECC)
2.3.4. Memory and I/O Organization x
2.3.4.1. Instruction and Data Buses 2.3.4.2. Address Map
2.3.4.1. Instruction and Data Buses x
2.3.4.1.1. Instruction Manager Port 2.3.4.1.2. Data Manager Port 2.3.4.1.3. Choosing a Suitable Interface
2.4. Programming Model x
2.4.1. Privilege Levels
2.5. Core Implementation x
2.5.1. Instruction Set Reference
3. Nios® V/m Processor x
3.1. Processor Performance Benchmarks 3.2. Processor Pipeline 3.3. Processor Architecture 3.4. Programming Model 3.5. Core Implementation
3.1. Processor Performance Benchmarks x
3.1.1. Pipelined 3.1.2. Non-pipelined
3.2. Processor Pipeline x
3.2.1. Pipelined Architecture 3.2.2. Non-pipelined Architecture
3.3. Processor Architecture x
3.3.1. General-Purpose Register File 3.3.2. Arithmetic Logic Unit 3.3.3. Reset and Debug Signals 3.3.4. Control and Status Registers 3.3.5. Trap Controller 3.3.6. Memory and I/O Organization 3.3.7. RISC-V based Debug Module 3.3.8. Error Correction Code (ECC)
3.3.5. Trap Controller x
3.3.5.1. Exception Handling 3.3.5.2. Interrupt Handling
3.3.5.2. Interrupt Handling x
3.3.5.2.1. Timer and Software Interrupt Module
3.3.6. Memory and I/O Organization x
3.3.6.1. Instruction and Data Buses 3.3.6.2. Address Map
3.3.6.1. Instruction and Data Buses x
3.3.6.1.1. Instruction Manager Port 3.3.6.1.2. Data Manager Port 3.3.6.1.3. Choosing a Suitable Interface
3.3.7. RISC-V based Debug Module x
3.3.7.1. Debug Mode 3.3.7.2. Halt from Debug Module 3.3.7.3. Trigger 3.3.7.4. Abstract Commands in Debug Mode 3.3.7.5. Hardware/Software Interface
3.4. Programming Model x
3.4.1. Privilege Levels 3.4.2. Control and Status Registers (CSR) Mapping
3.4.1. Privilege Levels x
3.4.1.1. Machine Mode (M-mode) 3.4.1.2. Debug Mode (D-mode)
3.4.2. Control and Status Registers (CSR) Mapping x
3.4.2.1. Control and Status Register Field
3.5. Core Implementation x
3.5.1. Instruction Set Reference
4. Nios® V/g Processor x
4.1. Processor Performance Benchmarks 4.2. Processor Pipeline 4.3. Processor Architecture 4.4. Programming Model 4.5. Core Implementation
4.3. Processor Architecture x
4.3.1. General-Purpose Register File 4.3.2. Arithmetic Logic Unit 4.3.3. Multipy and Divide Units 4.3.4. Floating-Point Unit 4.3.5. Custom Instruction 4.3.6. Reset and Debug Signals 4.3.7. Control and Status Registers 4.3.8. Trap Controller 4.3.9. Memory and I/O Organization 4.3.10. RISC-V based Debug Module 4.3.11. Error Correction Code (ECC) 4.3.12. Branch Prediction 4.3.13. Lockstep Module
4.3.4. Floating-Point Unit x
4.3.4.1. IEEE 754 Exception Conditions 4.3.4.2. Floating Point Operations
4.3.4.2. Floating Point Operations x
4.3.4.2.1. Floating Point Classification
4.3.8. Trap Controller x
4.3.8.1. Exception Controller 4.3.8.2. Interrupt Controller
4.3.8.2. Interrupt Controller x
4.3.8.2.1. Timer and Software Interrupt Module
4.3.9. Memory and I/O Organization x
4.3.9.1. Instruction and Data Buses 4.3.9.2. Address Map 4.3.9.3. Cache Memory 4.3.9.4. Tightly Coupled Memory
4.3.9.1. Instruction and Data Buses x
4.3.9.1.1. Instruction Manager Port 4.3.9.1.2. Data Manager Port
4.3.9.3. Cache Memory x
4.3.9.3.1. Instruction Cache 4.3.9.3.2. Data Cache 4.3.9.3.3. Configurable Cache Memory 4.3.9.3.4. Bypassing Cache (Peripheral Region) 4.3.9.3.5. Using Cache Memory Effectively
4.3.9.4. Tightly Coupled Memory x
4.3.9.4.1. Instruction and Data Tightly Coupled Memory 4.3.9.4.2. Accessing Tightly Coupled Memory 4.3.9.4.3. Using Tightly Coupled Memory Effectively
4.3.10. RISC-V based Debug Module x
4.3.10.1. Debug Mode 4.3.10.2. Halt from Debug Module 4.3.10.3. Trigger 4.3.10.4. Abstract Commands in Debug Mode 4.3.10.5. Hardware/Software Interface
4.3.11. Error Correction Code (ECC) x
4.3.11.1. ECC Interface 4.3.11.2. ECC Error Injection 4.3.11.3. Affected CSR during ECC Event
4.4. Programming Model x
4.4.1. Privilege Levels 4.4.2. Control and Status Registers (CSR) Mapping
4.4.1. Privilege Levels x
4.4.1.1. Machine Mode (M-mode) 4.4.1.2. Debug Mode (D-mode)
4.4.2. Control and Status Registers (CSR) Mapping x
4.4.2.1. Control and Status Register Field
4.5. Core Implementation x
4.5.1. Instruction Set Reference
1. Overview
2. Nios® V/c Processor
3. Nios® V/m Processor
4. Nios® V/g Processor
5. Nios V Processor Reference Manual Archives
6. Document Revision History for the Nios® V Processor Reference Manual

4.4.2. Control and Status Registers (CSR) Mapping

Control and status registers report the status and change the behavior of the processor. Since the processor core only supports M-mode and D-mode, Nios® V/g processor implements the CSRs supported by these two modes.

Table 91.  Control and Status Registers List
Number Privilege Name Description
Floating-Point CSRs
0x001 MRW fflags Floating-Point Accrued Exceptions. Refer to Floating-Point CSR Register Fields table.
0x002 MRW frm Floating-Point Dynamic Rounding Mode. Refer to Floating-Point CSR Register Fields table.
0x003 MRW fcsr Floating-Point Control and Status Register (frm and fflags). Refer to Floating-Point CSR Register Fields table.
Machine Trap Setup
0x300 MRW mstatus Machine status register. Refer to Machine Status Register Fields table.
0x301 MRW misa ISA and extensions. Refer to Machine ISA Register Fields table.
0x304 MRW mie Machine interrupt-enable register. Refer to Machine Interrupt-Enable Register Fields table.
0x305 MRW mtvec Machine trap-handler base address. Refer to .Machine Trap-Handler Base Address Register Fields table.
Machine Trap Handling
0x341 MRW mepc Machine exception program counter. Refer to Machine Exception Program Counter Register Fields table.
0x342 MRW mcause Machine trap cause. Refer to Machine Trap Cause Register Fields table.
0x343 MRW mtval Machine bad address or instruction. Refer to Machine Trap Value Register Fields table.
0x344 MRW mip Machine interrupt pending. Refer to Machine Interrupt-Pending Register Fields table.
0x348 MRW mtval2 Machine bad guest physical address. Refer to Machine Trap Value 2 Register Fields table.
Trigger Registers
0x7A0 MRW tselect Trigger select. Refer to Trigger Select Register Fields table.
0x7A1 MRW tdata1 (mcontrol) Trigger data 1 (Match Control). Refer to Trigger Data 1 (Match Control) Register Fields table.
0x7A2 MRW tdata2 Trigger data 2. Refer to Trigger Data 2 Register Fields table.
0x7A4 MRO tinfo Trigger info. Refer to Trigger Info Register Fields table.
Debug Mode Registers
0x7B0 DRW dcsr Debug control and status register. Refer to Debug Control and Status Register Fields table.
0x7B1 DRW dpc Debug Program Counter. Refer to Debug Program Counter Register Fields table.
Machine Information Register
0xF11 MRO mvendorid Vendor ID. Refer to Vendor ID Register Fields table.
0xF12 MRO marchid Architecture ID. Refer to Architecture ID Register Fields table.
0xF13 MRO mimpid Implementation ID. Refer to Implementation ID Register Fields table.
0xF14 MRO mhartid Hardware thread ID. Refer to Hardware Thread ID Register Fields table.

Section Content
Control and Status Register Field

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